JPS6238615A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To quicken the leading and to avoid much deterioration of the degree of circuit integration by combining an N-N type output buffer and a P-N type output buffer and using transistors (TR) at the pull-down side in common use for the both. CONSTITUTION:A P-channel MOS TR Q1 and an N-channel MOS TR Q2 constitute the P-N type output buffer and CMOS inverters Q3, Q4 and N-channel MOS TRs Q5, Q2 constitute the N-N type output buffer and the TR Q2 is used in common for the both. The N-channel MOS TR Q5 having a large driving capability at the leading drives an output terminal load circuit and the beta of the TR Q5 decreases as the level of an output terminal OUT is increased to decrease the drive capability, the P-channel MOS TR Q1 drives the load circuit at this point of time to boost the level of the output terminal OUT up to a voltage Vcc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor circuits, and in particular to output sofa circuits for integrated circuits.

[Prior art and problems]

CMOS inverters are often used in sofa circuits to the output of integrated circuits. This results in p as shown in Figure 3(a).
Channel MO5 (MIS if converted to -M) transistor Q1 and n-channel MOS transistor are connected to power supply Vcc,
Connected in series between Vss (ground) and transistor Q
The series connection point of I and Q2 is set as the output terminal OUT, and the gates are commonly connected to the input terminal IN. The input IN (the same sign is used for both the input and the input end. The same goes for the output end) is H (
If high), transistor Q2 is on, Ql is off,
The output OUT is L (low), and if the input IN-h<L, the output OUT is H.

This CMOS inverter has an extremely simple configuration and low power consumption (Ql and Q2 are on/off reversed, so Ql
, the current passing through Q2 is used only during a transient period). However, when the input IN changes stepwise from L to H, the temporal change in the output OUT is as shown in Figure 3 (b), and the rise is Slow. This is because transistor Q+ is p-channel type,
This is because β is small and the load such as parasitic capacitance attached to the output terminal OUT cannot be sufficiently driven. Although this point can be improved by increasing the size of the transistor Q1, this becomes an obstacle to increasing the degree of integration.

Therefore, recently, n-channel MOS with large drive capacity has been developed.
Push-pull type cover sofas that also use transistors on the pull amplifier side are beginning to be used. FIG. 2 shows this output buffer, and the transistor Q5 on the pull amplifier side is of an n-channel type.

Since the n-channel transistor is on and off opposite to the p-channel transistor, a CMOS inverter Q3. Interpose Qt. In this way, the operation of an output buffer which is an inverter can be obtained. That is, if the input IN is H, the transistor Q2 is on, and since Q4 is on and Q3 is off, the gate of Q5 is closed, so the transistor Q5 is off and the output is L1.If the input IN is L, the output is O.
UT is H.

However, this output sofa uses an n-channel transistor Q5 on the pull-up side, so the output 01JT is high.
The level is lower than the voltage 11Vcc by the threshold voltage vth of the transistor Q5. In addition, since it is an n-channel transistor, it has a large drive capability and a fast rise time, but the H level V
As it approaches cc-Vth, it becomes dull and it takes time to reach the HL-bell. This is due to the bank gate effect. That is, as the level of the output OUT increases, the potential of the hack gate increases, β becomes smaller, and charging of the load capacitor becomes slower. Furthermore, if the H level of the output OUT is one step lower than Vth, for example, the load circuit is
This is an MO3 circuit, and if the input is not at a sufficiently high or low level, both the pull-up side and pull-down side transistors will be turned on, and Vcc and V will pass through these transistors.
Problems such as current flowing between ss and ss may occur.

The present invention aims to improve the above points and provide an output buffer circuit which has a fast rise time, does not have one step drop in Vth, and does not significantly deteriorate the degree of integration.

(Means for Solving the Problems) The semiconductor circuit of the present invention has a p-channel MOS transistor Ql and an n-channel MOS transistor Q2 connected in series, the series connection point being an output terminal, and the gates of these transistors being an input terminal. The present invention is characterized by comprising a CMOS inverter section having the same structure as above, and an n-channel MOS transistor Q5 which is connected in parallel with the p-channel MO3I transistor Q1 and has a gate to which a complementary signal of the input terminal is applied.

[Function and Examples]

As shown in FIG. 1, in the present invention, an nn-type output sofa and a pn-type output sofa are combined, and the pull-down side transistor Q2 is shared by both. That is, p-channel MOS transistor Q1 and n-channel MO3I
-Lanlista Q2 has a p-n type cover sofa shown in Fig. 3,
Also, CMOS inverter Q3. Q4 and n channel MO
3I-Run Lister Q5. Q2 constitutes the nn type output sofa shown in FIG. 2, and the transistor Q2 is shared by both.

This outcover sofa also operates on an inverter. That is, input I
If N is H, transistor Q2 is on, Ql is off, and Q3 is off and Q4 is on, so the gate of Q5 is at L level and Q! 1 is off, so the output is OUT. Input IN
If is L, the opposite is true, and the output OUT is H. This output O
H of UT rises quickly and rises to Vcc.

In other words, in the rising part, the n-channel MO3 with large driving capacity
The I-run risk Q5 drives the output terminal load circuit, and as the level of the output terminal OUT increases, β of the transistor Q5 decreases, and the driving capability decreases, but at this point, the p-channel MOS transistor Q1 drives the load circuit. , output O
Pull up UT to Vcc.

Figure 1(b) shows the rise characteristic of the output OUT, and the curve C
+ is the characteristic due to p-n output buffer section, curve C2 is n-
The characteristic curve C3 due to the n-output cover sofa section is the characteristic of the circuit shown in FIG. Curve C3 has a fast rise and rises to VCC.

[Effect of baldness]

As explained above, according to the present invention, it is possible to obtain an output sofa in which the H level rises quickly and rises to the power supply Vcc, and compared to the conventional circuit shown in FIG. Therefore, it does not hinder the improvement of the degree of integration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing a conventional example. In the drawing, QI is p-channel MO3I-run lister, Q2
is an n-channel MOS transistor, IN is the input terminal, O
UT is an output terminal, Q5 is an n-channel MOS +- run lister, Q3. QI is p, n that constitutes a CMOS inverter
Channel MO3I - Run lister.

Claims (1)

[Claims] A CMOS inverter section in which a p-channel MOS transistor Q_1 and an n-channel MOS transistor Q_2 are connected in series, with the series connection point as an output terminal and the gates of these transistors as an input terminal, and the p-channel MOS
A semiconductor circuit comprising an n-channel MOS transistor Q_5 connected in parallel with the transistor Q_1 and having a gate applied with a signal complementary to the input terminal.