JPS5935456A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminte instability in the case when the device is operated in parallel by making at least one terminals independent at every semiconductor element and connecting these terminals by a resistor when a plurality of the elements are encased in one vessel and electrode terminals connected to each input and output electrode are drawn outside the vessel. CONSTITUTION:A vessel 1 is constituted by a metallic base 1a and an insulator frame body 1b, two same transistor elements 4 are encased in the element encasing section of the vessel, a bonding metallic film 6a connected in common to drain electrodes as the output sides of the two elements 4 is formed to the upper surface of the frame body 1b, and a common electrode terminal 3 for external drawing is fitted to the film 6a. On the other hand, bonding films 6G made independent at every element 4 are formed on the gate electrode sides as input sides, gate electrode terminals 2 are made independent at every element 4 from the films 6G and drawn to the outside, and a resistance film 7 is connected between these terminals. Accordingly, a plurality of the elements are encased in the same vessel in order to increased as output from the device, and unstable elements in the case when the elements are operated in parallel are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a transistor device that is effective in ultra-high frequency bands.

In recent years, in order to increase the output power of semiconductor devices, a plurality of semiconductor elements or a semiconductor element having a plurality of cells are housed in the same container, and the output power is increased by parallel operation.

FIG. 1(a) is a plan view of a conventional field effect transistor.
Figure (b) is a sectional view taken along line AA in figure (&). Figure 1 (
In a) and (b), 1 & is a metal paste, which also serves as the bottom surface of the container and the source electrode terminal. 2 indicates a gate lead-out electrode terminal, and 3 indicates a drain lead-out electrode terminal. Reference numeral 4 indicates a semiconductor element, and reference numeral 5 indicates a thin metal wire for connecting the semiconductor element and an external lead-out electrode terminal.

When using such a semiconductor device by grounding it to the vtt-source electrode terminal 11', the output power of one semiconductor device may be low due to a long distance from the input electrode terminal 2 to the two semiconductor devices 4, 4, impedance mismatch, etc. Are you an idiot who can't get twice as much as you would?
In some cases, this may cause instability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that eliminates the unstable elements that conventional SEIZO has.

A semiconductor device of the present invention includes a plurality of semiconductor elements having input electrodes and output electrodes, a container that houses the semiconductor elements, and an electrode terminal that leads the electrodes of the semiconductor elements out of the container. , at least one side of the input or output electrode terminals is led out of the container independently for each element, and a resistor is provided between the electrode terminals.

Next, all embodiments of the present invention will be explained.

FIG. 2 is a plan view of one embodiment of the present invention. In FIG. 2, two identical transistor elements 4, 4 are housed in the element accommodating portion of a container 1 formed of a metal paste 1& and an insulating frame 1b, and on the upper surface of the container 10 frame 1b, A bonding metal film 6d on the output electrode side, that is, the drain electrode side, is provided, and the metal film 6d is commonly connected to the drain electrodes of the two elements 4.4, and a common electrode terminal 3 is drawn out to the outside. There is. On the other hand, on the input electrode side, that is, on the gate electrode side, there are bonding metal films 6G, 6G independently connected to the elements 4, 4;
Gate electrode terminals 2.2 are independently drawn out from 6G for each element. Further, the metal films 6G and 6G are connected by a resistive film 7.

FIG. 3 is a plan view of the semiconductor device v of the present invention shown in FIG. 2 applied to an actual circuit. In FIG. 3, 8 and 9 are an input circuit section and an output circuit section, respectively, each having a microstrip line configuration, and 10 is a semiconductor device shown in FIG. 2. In FIG. 3, the input signal power is input to the input circuit section 8.
The signal is input to the strip line, divided into two by seven Y-shaped branch lines, and input independently to two semiconductor devices.

Now, if there is a difference in the input impedance of the two semiconductor elements, the reflection coefficients will be different and a potential difference will occur between both lines at the input end. This potential difference is applied across a resistor connected inside the container, causing current to flow through the resistor and reducing the potential difference between both lines. Therefore, instability caused by imbalance between semiconductor elements can be eliminated. In this case, the branch line length needs to be about 1/4 wavelength. Moreover, an impedance matching circuit can also be provided on each branch line.

The present invention is particularly effective for high frequency, high power semiconductor devices. In the above embodiment, the case where the present invention is applied to a source grounded type and field effect type transistor has been described, but it can also be applied to other grounded types and bipolar transistors. The number of branches can also be increased by changing the number of elements or cells. The resistance value is determined by the trade-off between high frequency loss and stability, but is preferably 2 to 10 times the ripple component of the input impedance.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a conventional semiconductor device, and FIG. 1(b) is a plan view of a conventional semiconductor device.
2 is a plan view of an embodiment of the present invention, and FIG. 3 is a semiconductor device of the present invention. FIG. 3 is a plan view showing an example of actual use. 1...Container, 1a...Metal base,
1b... Frame body, 2... Gate electrode terminal, 3... Drain electrode terminal, 4... Semiconductor element, 5... Metal Thin line, 6d...
Drain side metal film, 6G...Gate side metal film,
7...Resistor, 8...Input circuit section, 9.
・・・・・・Output ￥3Ilii]

Claims (1)

[Claims] Completely equipped with a plurality of semiconductor elements having input electrodes and output electrodes, a container housing these semiconductor elements together, and a plurality of electrode terminals connected to the input electrodes and output electrodes respectively and led out of the container, Among these electrode terminals, at least one electrode terminal on the input electrode side or the output electrode side is independent for each element, and the independent electrode terminals are connected by a resistor. semiconductor devices.