JPS5935447A - Breaking method for semiconductor wafer - Google Patents

Breaking method for semiconductor wafer

Info

Publication number
JPS5935447A
JPS5935447A JP57146386A JP14638682A JPS5935447A JP S5935447 A JPS5935447 A JP S5935447A JP 57146386 A JP57146386 A JP 57146386A JP 14638682 A JP14638682 A JP 14638682A JP S5935447 A JPS5935447 A JP S5935447A
Authority
JP
Japan
Prior art keywords
wafer
sheet
elements
semiconductor wafer
braking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57146386A
Other languages
Japanese (ja)
Inventor
Takashi Honda
本多　孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP57146386A priority Critical patent/JPS5935447A/en
Publication of JPS5935447A publication Critical patent/JPS5935447A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To aviod collisions among elements after breaking, and to prevent the generation of broken pieces by dicing the semiconductor wafer into each element, pasting the wafer to a sheet, stretching the sheet to the outside centering around the wafer and breaking the wafer. CONSTITUTION:A semiconductor wafer 12 is diced into each element, and the wafer 12 in which one surface is still connected is pasted on the sheet 11. When these elements are broken, the wafer 12 is surrounded by a sheet fixing ring 9 without breaking them by using a roller, and the sheet 11 is stretched to the outside centering around the wafer 12 to isolate each element. Accordingly, the divided elements 17, 18, etc. do not collide, and cracks and broken pieces and the like are not generated in the elements 17, 18.

Description

【発明の詳細な説明】 この発明は、半導体ウェハーをダイシング後シートに貼
り付は各素子にブレーキングする方式に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of pasting a semiconductor wafer onto a sheet after dicing and braking each element.

従来は、シート貼り付は後、ローラーにてブレーキング
を行っているが、ブレーキング後の素子を貼り付けたシ
ートの取り扱いで素子と素子がぶつかり、素子のカケを
発生させるという欠点があった。Conventionally, after pasting the sheet, braking was performed using a roller, but this had the disadvantage that when handling the sheet with the elements pasted after braking, the elements collided with each other, causing chipping of the elements. .

即ち、第１図に示す如〈従来はダイシング後のウェハー
２をシート１へ貼り付け、ウェハー表面保護シート３を
行いクッション５へ乗せて、上よリローラ４に荷重をか
けながらブレーキングを行っていた。ブレーキング後、
ブレーキングされた素子を貼ったシートの取り扱い上第
２図の示す様にたわむ場合がある。シートがたわむと素
子７と素子８がぶつかり合いカケの原因と成っている。That is, as shown in Fig. 1, conventionally, a wafer 2 after dicing is attached to a sheet 1, a wafer surface protection sheet 3 is applied, the wafer is placed on a cushion 5, and braking is performed while applying a load to the reroller 4. Ta. After braking,
When handling a sheet with a braked element pasted on it, it may bend as shown in Figure 2. When the sheet bends, elements 7 and 8 collide, causing breakage.

この発明の目的は、前述した従来のブレーキングとは異
なった方式であり、ブレーキング後の素子間のぶつかり
合いによるカケの発生をなくす方式を提供することにあ
る。An object of the present invention is to provide a method that is different from the conventional braking method described above and eliminates the occurrence of chips due to collisions between elements after braking.

本発明の特徴は半導体ウェハーを各素子にダイシング後
シートに貼り付はウェハーを中心に外側にシートを引き
伸ばしブレーキングする方式にある。The feature of the present invention is that after dicing a semiconductor wafer into individual elements, the sheet is attached to a sheet by stretching the sheet outward from the wafer and applying a brake.

第３図および第４図はこの発明の一実施例を説明する為
の上面図である。即ち本発明のブレーキング方式は、第
２図のようにローラでブレーキングするのではなく、第
３図に示す如くブレーキング前に半導体ウェハー１２を
中心にシート２１を均等に引っばりリング９に固定し、
第１図の様にしてブレーキングする方式である。FIGS. 3 and 4 are top views for explaining one embodiment of the present invention. That is, the braking method of the present invention does not use rollers to brake as shown in FIG. 2, but as shown in FIG. fixed,
This is a method of braking as shown in Figure 1.

その結果第４図に示す如くブレーキング後は素子１７と
素子１８は離れ、ぶつかり合いによるカケの発生はなく
なり、取り扱いも容易に成った。As a result, as shown in FIG. 4, the elements 17 and 18 are separated after braking, eliminating the occurrence of chips due to collision and making handling easier.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来技術を示すもので。 第１図は半導体ウェハーをダイシングし、シート貼り付
は後のブレーキング方式の断面図で、第２図は、ブレー
キング後取り扱いで発生するカケのメカニズムを示した
断面図である。 第３図および第４図は本発明の実施例を示すもので第３
図は半導体ウェハーをブレーキング前にシートを引き伸
ばしリングで固定させた上面図であり、第４図はダイシ
ング後の半導体ウェハーのブレーキング後の半導体素子
の上面図である。 尚、図に於いて、１．１１・・・・・・シー）、２．１
２・・・・・・ダイシング後のウェハー、３・・・・・
・保護シート、４・・・・・・ブレーキング用ローラ、
５・・・・・・ブレーキング用りッシ９ン、６・・・・
・・ダイシング跡、７．８・・・・・・ブレーキング後
の素子、９・・・・・・シート固定リング。1 and 2 show the prior art. FIG. 1 is a cross-sectional view of a braking method after dicing a semiconductor wafer and pasting a sheet, and FIG. 2 is a cross-sectional view showing the mechanism of chipping that occurs during handling after braking. 3 and 4 show embodiments of the present invention.
The figure is a top view of a semiconductor wafer with a sheet fixed with a stretching ring before breaking, and FIG. 4 is a top view of a semiconductor element after breaking the semiconductor wafer after dicing. In addition, in the figure, 1.11...C), 2.1
2...Wafer after dicing, 3...
・Protection sheet, 4...braking roller,
5...Breaking switch 9, 6...
... Dicing marks, 7.8 ... Element after braking, 9 ... Seat fixing ring.

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハーを各素子にダイシング後シートに貼り付
け、ウェハーを中心に外側にシートを引き伸ばしブレー
キングすることを特徴とする方式。This method is characterized by dicing a semiconductor wafer into each element and attaching it to a sheet, then stretching the sheet outward from the wafer and applying braking.
JP57146386A 1982-08-24 1982-08-24 Breaking method for semiconductor wafer Pending JPS5935447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57146386A JPS5935447A (en) 1982-08-24 1982-08-24 Breaking method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57146386A JPS5935447A (en) 1982-08-24 1982-08-24 Breaking method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5935447A true JPS5935447A (en) 1984-02-27

Family

ID=15406524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57146386A Pending JPS5935447A (en) 1982-08-24 1982-08-24 Breaking method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5935447A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009020245A2 (en) * 2007-08-07 2009-02-12 Panasonic Corporation Method of segmenting semiconductor wafer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009020245A2 (en) * 2007-08-07 2009-02-12 Panasonic Corporation Method of segmenting semiconductor wafer
WO2009020245A3 (en) * 2007-08-07 2009-03-26 Panasonic Corp Method of segmenting semiconductor wafer
US8110481B2 (en) 2007-08-07 2012-02-07 Panasonic Corporation Method of segmenting semiconductor wafer

Similar Documents

Publication Publication Date Title
EP0392399A3 (en) Method and apparatus for wafer transfer
US5920769A (en) Method and apparatus for processing a planar structure
CA2113019A1 (en) Integrated partial sawing process
CA2050781A1 (en) Process for preparing semiconductor device
JPS5935447A (en) Breaking method for semiconductor wafer
CA2351757A1 (en) Method device for winding metal strips
JPH01276740A (en) Pelletizing method
WO1999048137A3 (en) Method and device for treating wafers presenting components during thinning of the wafer and separation of the components
JP2752643B2 (en) Method for manufacturing semiconductor device
JPS63276240A (en) Manufacture of semiconductor device
JP2019071495A5 (en)
KR940000745B1 (en) Wire bonding method
JPH05259277A (en) Manufacture of semiconductor device
US20080116533A1 (en) Semiconductor device in wafer assembly
JPS5934643A (en) Braking method for semiconductor wafer
JPS6329948A (en) Manufacture of semiconductor device
JPH05198671A (en) Dicing method of semiconductor wafer
JPS63200544A (en) Semiconductor wafer breaker
JPH0529455A (en) Manufacturing method of semiconductor device
US20050147489A1 (en) Wafer supporting system for semiconductor wafers
JPS62152814A (en) Method of dicing semiconductor wafer
JPS5980940A (en) Manufacture of insulator isolated substrate
JP7216504B2 (en) Expanding method
JPH03180049A (en) Method for picking up semiconductor device
JPS58142543A (en) Dicing method for semiconductor substrate