JPS5934643A - Braking method for semiconductor wafer - Google Patents

Braking method for semiconductor wafer

Info

Publication number
JPS5934643A
JPS5934643A JP57145655A JP14565582A JPS5934643A JP S5934643 A JPS5934643 A JP S5934643A JP 57145655 A JP57145655 A JP 57145655A JP 14565582 A JP14565582 A JP 14565582A JP S5934643 A JPS5934643 A JP S5934643A
Authority
JP
Japan
Prior art keywords
sheet
wafer
braking
wafers
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57145655A
Other languages
Japanese (ja)
Inventor
Takashi Honda
本多 孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP57145655A priority Critical patent/JPS5934643A/en
Publication of JPS5934643A publication Critical patent/JPS5934643A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

PURPOSE:To reduce the generation of the broken pieces and flaws of each element, and to decrease man-hours by pasting a sheet and a wafer while braking the wafer. CONSTITUTION:Wafers 2 after dicing are placed on the protective sheet 9, and the wafers are covered with the sheet 1. Each element is broken and the sheet 1 and the backs of each element of the wafers are pasted at the same time while applying fixed load to a braking roller 7.

Description

【発明の詳細な説明】 この発明は、半導体ウェハーのダイシング後のブレーキ
ングする方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for braking a semiconductor wafer after dicing.

従来は、ウェハー裏面をシート側に、表面をセパレータ
ー仰]にセットし、それを回転している2個のゴムロー
ラ間に適すことにより、シートとウェハー裏面の気泡を
抜きながらシートとウェハー裏面を貼り付ける。その後
、ブレーキング時セパレーターとシートに貼り付けられ
たウェハーに於いてセパレーターを剥がし、そのウェハ
ー表面を保護するシートで気泡ができない様カバーし、
保護シート及びウェハー表面全クッション側に置き、ダ
イシングラインと平行に金属のローラに一定の荷重を加
え、ローラを回転させながら各素子にブレーキングを行
っているが、シート貼p付は工程及び取り扱いによりウ
ェハーがダイシングラインよシワレ易い。そのワレによ
ジ各素子のカケ不良の発生やワレによシシリコン層が良
品素子へ移動付着し、ブレーキングすることでキズ不良
も発生させるという欠点があった。
Conventionally, the back side of the wafer was set on the sheet side, and the front side was placed on the separator side, and the wafer was placed between two rotating rubber rollers.The sheet and the back side of the wafer were pasted together while removing air bubbles from the back side of the sheet and wafer. wear. After that, during braking, the separator was removed from the wafer attached to the separator and sheet, and the wafer surface was covered with a protective sheet to prevent air bubbles from forming.
A protective sheet and the entire wafer surface are placed on the cushion side, and a certain load is applied to a metal roller parallel to the dicing line, and each element is braked while rotating the roller, but the process and handling of attaching the sheet is difficult. The wafer is easily wrinkled along the dicing line. This cracking causes chipping defects in each element, and the cracking causes the silicon layer to move and adhere to non-defective devices, resulting in scratches caused by braking.

即ち、第1図に示す如〈従来は、ダイシング後のウェハ
ー2のダイシングした3の方をシートのセパレーター4
側にしシート1とではさみ、第1図の様な方向に回転す
るゴムローラ5と6間を通し、シート1とウェハー4の
裏面の気泡を抜きながらシート1をウェハー4の裏面に
貼り付ける。
That is, as shown in FIG.
The sheet 1 is sandwiched between the sides of the sheet 1 and passed between rubber rollers 5 and 6 rotating in the direction shown in FIG. 1, and the sheet 1 is pasted on the back surface of the wafer 4 while removing air bubbles from the back surfaces of the sheet 1 and the wafer 4.

その後、セパレーターe[がし、第2図に示す如く、ウ
ェハーサイズよりやや太き♂シート9の上にシートlに
貼ら扛たウェハー2を気泡が出来ない様にして乗せる。
Thereafter, the separator e is removed, and the wafer 2 pasted on the sheet l is placed on the female sheet 9, which is slightly thicker than the wafer size, as shown in FIG.

そしてブレーキング7に一定の荷重をかけながら各素子
へ分割していた。ゴムローラー間を通しシート1とウェ
ハー2の裏面を貼シ付ける時及びウェハーよりシートの
サイズが倍程大きい為取り扱い時ウェハーが割れ易い。
Then, while applying a constant load to the brake 7, it was divided into each element. When pasting the back sides of sheet 1 and wafer 2 through rubber rollers, and because the size of the sheet is twice as large as that of the wafer, the wafer tends to break when handled.

ナの割れによる各素子のカケ不良の発生やワレによるシ
リコン屑が良品素子へ移動、付着した状態でブレーキン
グするとキズ不良を発生させる原因と成っている。
Cracks in each element can cause chipping defects in each element, and silicon debris from cracks can migrate to and adhere to good elements, causing scratches when braking.

この発明の目的は前述したブレーキングとは異なった方
法であり、ブレーキング前のウニ/・−ワレの工程即ち
シートとウニノ・・−の貼り付は工程を省き、ブレーキ
ングまでの取り扱いによるダイシングラインからのウェ
ハーワレをなくシ、ブレーキングを行いながらシートと
ウェハーを貼り付ける方式である。
The purpose of this invention is to provide a method different from the above-mentioned braking, in which the process of pasting the sea urchin and sea urchin before braking, that is, the process of pasting the sheet and the sea urchin, is omitted, and dicing is performed by handling before braking. This method eliminates wafer cracks from the line and attaches the sheet and wafer while applying braking.

即ち第2図の様に保護シート9の上にダイシング後のウ
ェハー2をb’aき、その上にシート1をカバーした後
ブレーキングローラ7に一定の荷重をかけながら各素子
へブレーキングと同時にシート1とウェハー2の各素子
の裏面を貼9つける方式である。その結果ウェハーワレ
による各素子のカケ及びキズの発生が減少し、一工程省
略することで工数低減と成った。
That is, as shown in FIG. 2, the diced wafer 2 is placed on a protective sheet 9, and after covering the sheet 1 thereon, each element is braked while applying a constant load to the braking roller 7. At the same time, the back surfaces of each element on the sheet 1 and the wafer 2 are pasted 9. As a result, the occurrence of chips and scratches on each element due to wafer cracking was reduced, and the number of man-hours was reduced by omitting one step.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、ダイシングされたウェハーをシートとセパレ
ーター間にセットし、ゴムローラー間ヲ通し、ウェハー
裏面とシートを貼り付ける工程の断面図である。第2図
はセパレーターを剥がし。 保護シートの上にシートに貼り付けられたウェハーをセ
ットし、ブレーキングする工程の断面図である。又保護
シートの上にウェハーをセットし。 その上にシートラセット後、ブレーキングする工程の断
面図でもある。 同図に於いて、1・・・・・・サイズの大きいシート。 2・・・・・・ダイシングされたウェハー% 3・・・
・・ダイシフ/跡%  4・・・・・・シートのセパレ
ーター、5,6・・・ゴムローラー、7・・・・・・ブ
レーキングローラ、8・・・・・・クッション、9・・
・・・・保護シート。
FIG. 1 is a cross-sectional view of the process of setting a diced wafer between a sheet and a separator, passing it through between rubber rollers, and pasting the sheet to the back surface of the wafer. Figure 2 shows the separator removed. FIG. 3 is a cross-sectional view of a process of setting a wafer attached to a protective sheet on a protective sheet and braking the same. Also, set the wafer on the protective sheet. It is also a sectional view of the process of braking after the seat truss is set. In the same figure, 1... is a large sheet. 2...Diced wafer% 3...
...Die shift/mark percentage 4...Sheet separator, 5, 6...Rubber roller, 7...Breaking roller, 8...Cushion, 9...
...protective sheet.

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハーを各素子にダイシング後、ウェハーにシ
ートを貼り付ける工程と各素子にブレーキングを施す工
程とを同時に行うことを特徴とする半導体ウェハーのブ
レーキング方式。
A braking method for semiconductor wafers that is characterized in that after dicing a semiconductor wafer into individual elements, the process of attaching a sheet to the wafer and the process of applying braking to each element are performed simultaneously.
JP57145655A 1982-08-23 1982-08-23 Braking method for semiconductor wafer Pending JPS5934643A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57145655A JPS5934643A (en) 1982-08-23 1982-08-23 Braking method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57145655A JPS5934643A (en) 1982-08-23 1982-08-23 Braking method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5934643A true JPS5934643A (en) 1984-02-25

Family

ID=15390030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57145655A Pending JPS5934643A (en) 1982-08-23 1982-08-23 Braking method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5934643A (en)

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