JPS593501A - Control device - Google Patents
Control deviceInfo
- Publication number
- JPS593501A JPS593501A JP57114274A JP11427482A JPS593501A JP S593501 A JPS593501 A JP S593501A JP 57114274 A JP57114274 A JP 57114274A JP 11427482 A JP11427482 A JP 11427482A JP S593501 A JPS593501 A JP S593501A
- Authority
- JP
- Japan
- Prior art keywords
- output
- cpu
- timer
- processing unit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は中央処理装置（以下ＣＰＵと称する。）を備え
、内燃機関等の制御に用いられる制御装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device that includes a central processing unit (hereinafter referred to as CPU) and is used to control an internal combustion engine or the like.
近年、内燃機関等の制御装置としてＣＰＵを備えた制御
装置が用いられておシ、とのＣＰＵは周知のように予め
記憶手段に定められた手順に従って入力条件に応じた演
算を行うとともに少くとも一つ以上の制御対象に対して
制御出力を行うのが通例である。ところで、例えば内燃
機関の制御装置に用いられるＣＰＵは使用上強電磁界の
存在する地域を走行したりあるいは同−車両内において
強電磁界を発生する機器と近接して設置される場合が少
くない。このため、ＣＰＵは一時的な強電磁界によって
誤動作することがあり、このような場合には予め記憶り
段に定められた手順に従えなくなり、出力が不定となっ
て制御対象の動作が異常になるといった不具合が生じた
。そこで、従来ではこのような不具合を解消するためＣ
ＰＵが正常に動作しているか否かを判定する外部回路を
設け、この外部回路がＣＰＵの異常を検出すると該回路
からＣＰＵの初期起動端子（以下Ｒｅ５ｅｔ端子と称す
る。）に信号を加えてＣＰＵが予め記憶手段に定められ
た手順の最初から実行できるように再起動を行い、一時
的な要因による誤動作が永久に接続することがないよう
にしていた。In recent years, control devices equipped with a CPU have been used as control devices for internal combustion engines, etc. As is well known, the CPU performs calculations according to input conditions according to procedures set in advance in a storage means, and at least performs calculations according to input conditions. It is customary to provide control output to one or more controlled objects. By the way, for example, a CPU used in a control device for an internal combustion engine is often driven in an area where a strong electromagnetic field exists or is installed in the same vehicle in close proximity to equipment that generates a strong electromagnetic field. For this reason, the CPU may malfunction due to temporary strong electromagnetic fields, and in such cases, it will no longer be able to follow the procedures predetermined in the memory stage, resulting in unstable output and abnormal operation of the controlled object. A problem occurred. Therefore, in the past, in order to solve this problem, C
An external circuit is provided to determine whether or not the PU is operating normally, and when this external circuit detects an abnormality in the CPU, a signal is applied from the circuit to the initial startup terminal (hereinafter referred to as the Re5et terminal) of the CPU to restart the CPU. The device is restarted so that it can be executed from the beginning of the procedure predetermined in the storage means, so that malfunctions caused by temporary factors will not become permanent.
上記のような従来の内燃機関用制御装置を第１図に示す
。図において、１は予め定められた演算手順が格納され
る不揮発性記憶手段、演算子一段、演算処理における中
間値又は最終値を読み取シ書き込み可能な記憶手段およ
び入出力ボート等を内蔵したＣＰＵで、ＣＰＵＩは入力
端子としてＲｅ５ｅｔ端子を有するとともに出力端子と
してＰＯＷ、ＰＯＧ 。A conventional internal combustion engine control device as described above is shown in FIG. In the figure, 1 is a CPU that has a built-in non-volatile storage means for storing predetermined calculation procedures, one stage of operators, a storage means that can read and write intermediate values or final values in calculation processing, and an input/output board. , CPUI has a Re5et terminal as an input terminal, and POW and POG as output terminals.
ＰＯＣの各端子を有する。２は該制御装置に電源を印加
した際に一過性の信号を出力するパワーオンリセット部
（以下ＦＯＲと称する。）、３はＰＯＷ端子の出力を入
力され、ＣＰＵＩが正常に動作しているか否かを判定す
るウォッチドッグタイマ部（第１の時限手段、以後ＷＤ
Ｔと称する。）、４はＰＯＲ２の出力およびＷＤＴ３の
出力を入力されるとともに出力をＲｅ５ｅｔ端子に入力
するＯＲ手段、７はＰＯＧ端子の出力およびＯＲ手段４
の出力を入力されるＮＯＲ手段、６はＰＯＣ端子の出力
およびＮＯＲ手段７の出力を入力されるとともに出力を
内燃機関における制御対象５に入力するＡＮＤ手段であ
る。It has each terminal of POC. 2 is a power-on reset unit (hereinafter referred to as FOR) that outputs a temporary signal when power is applied to the control device, and 3 is a unit that receives the output of the POW terminal and checks whether the CPU is operating normally. A watchdog timer unit (first timer means, hereinafter referred to as WD) that determines whether
It is called T. ), 4 is an OR means that receives the output of POR2 and the output of WDT3 and inputs the output to the Re5et terminal, 7 is the output of the POG terminal and OR means 4
The NOR means 6 receives the output of the POC terminal and the output of the NOR means 7, and is an AND means that inputs the output to the controlled object 5 in the internal combustion engine.
次に上記装置の動作を第２図のタイミングチャートを用
いて説明する。ｆず、この制御装置に電源が印加される
と第２図に）に示すようにＦＯＲ２は一過性のｒＨＪ信
号を出力し、このためＯＲ手段４を介してＲｅ５ｅｔ端
子にｒＨＪ信号が加えられ、これによってＣＰＵＩは初
期起動するとともに各出力端子ＰＯＷ、ＰＯＧ、ＰＯＣ
はｒＬＪとなる。初期起動後、ＣＰＵＩは予め定められ
た手順に従って図示しない入力に応じて演算を行い、Ｐ
ＯＣ端子から制御対象５に対する制御信号を出力するが
、第２図（へ）に示すように入力に応じた制御信号を演
算するのに要する演算時間△ｔの間は制御信号が不定と
なる。Next, the operation of the above device will be explained using the timing chart of FIG. When power is applied to this control device, FOR2 outputs a transient rHJ signal as shown in FIG. , this causes the CPU to initially start up and connects each output terminal POW, POG, POC.
becomes rLJ. After initial startup, the CPUI performs calculations according to inputs (not shown) according to predetermined procedures, and
A control signal for the controlled object 5 is output from the OC terminal, but as shown in FIG.
このため、ＣＰＵＩは△ｔの間は第２図（ホ）に示すよ
うにＰＯＧ端子から［−Ｈ」信号を出し、これによって
ＮＯＲ手段７の出力は１−ＬＪとな夛、ＡＮＤ手段６の
出力がｒＬＪとなって制御信号は制御対象５に加わらな
い。Therefore, during Δt, the CPU outputs a [-H] signal from the POG terminal as shown in FIG. The output becomes rLJ and no control signal is applied to the controlled object 5.
この△を以後はＰＯＧ端子の出力はｒＬＪとなるのでＡ
ＮＤ手段６の出力が田」となシ、制御信号が制御対象５
に加わる。又、ＣＰＵ１が予め定められた手順に従って
正しく演算処理を行っている間はＰＯＷ端子からは所定
時間以内に田」とｒＬＪが反転する信号が出力される。After this △, the output of the POG terminal becomes rLJ, so A
The output of the ND means 6 is 1, and the control signal is the control target 5.
join. Further, while the CPU 1 is correctly performing arithmetic processing according to a predetermined procedure, a signal in which rLJ is inverted is output from the POW terminal within a predetermined time.
ＷＤＴ３はＰＯＷ端子の出力が反転する毎にトリガされ
てＴ。秒間のｒＬＪ出力を行う再トリガ可能な単安定発
振器を含んで構成さ−れ、例えば第２図（ロ）に示すよ
うにＰＯＷ端子の反転出力がＴ。秒間とだえると、第２
図（ハ）に示すようにｒＨＪ出力を行う。ＷＤＴ３の時
限１０秒間はＣＰＵＩのｐｏｗ端子の反転周期より長く
しであるため、ＣＰＵ１が予め定められた手順に従って
正常に演算処理を行っている間はＷＤＴ３の出力が川」
となることはないが、強電磁界等によシ誤動作してＰＯ
Ｗ端子の出力が反転できなくなるとＴ。秒後にはＷＤＴ
３の出力がｒＨＪとなり、ＯＲ手段４を介してＣＰＵＩ
のＲｅ５ｅｔ端子に［１月信号が加わり、ＣＰＵＩは再
起動されて正規の演算手順に復帰すΣ。このように従来
装置ではＣＰＵＩの動作を監視するＷＤＴ３の出力によ
シＣＰＵＩの再起動を行っている。ために一時的な強電
磁界等により誤動作が永久に持続することはない。WDT3 is triggered every time the output of the POW terminal is inverted. It is configured to include a retriggerable monostable oscillator that outputs rLJ for seconds. For example, as shown in FIG. 2 (b), the inverted output of the POW terminal is T. After a few seconds, the second
rHJ output is performed as shown in Figure (c). The 10 second time limit of WDT3 is longer than the reversal period of the pow terminal of the CPUI, so while the CPU1 is normally performing arithmetic processing according to a predetermined procedure, the output of WDT3 is low.
However, due to strong electromagnetic fields, etc., it may malfunction and cause PO.
T when the output of the W terminal can no longer be inverted. WDT in seconds
The output of 3 becomes rHJ and is sent to the CPU via OR means 4.
The January signal is added to the Re5et terminal of Σ, and the CPU is restarted and returns to the normal calculation procedure. In this way, in the conventional device, the CPUI is restarted based on the output of the WDT 3 that monitors the operation of the CPUI. Therefore, malfunctions will not persist permanently due to temporary strong electromagnetic fields.
しかるに、ＣＰＵＩが故障等により定常的に正常な演算
処理ができない場合には、ＷＤＴ３の出力によ、！１）
ＣＰＵＩが再起動された後に再びＴ。秒後にＣＰＵＩは
再起動されることになり、との１０秒間においては第２
図（ホ）、（へ）に示すようにＰＯＧおよびＰＯＣ端子
からの出力は不定であシ、制御対象５はＴ。秒間の異常
な制御をサイクリックに行われることになる。However, if the CPU is unable to perform normal arithmetic processing due to a malfunction, etc., the output of the WDT3 will be used. 1)
T again after the CPUI is restarted. The CPUI will be restarted after 10 seconds, and the second
As shown in Figures (E) and (F), the outputs from the POG and POC terminals are undefined, and the controlled object 5 is T. Abnormal control for seconds will be performed cyclically.
本発明は上記の従来の欠点を除去するために成されたも
のであり、ＣＰＵの一時的な誤動作が永久に持続するこ
とがなく、又ＣＰＵが定常的に正常な演算処理ができな
いときには制御信号が制御対象に加わらないようにして
フ王イルセイフの設定を容易にした制御装置を提供する
ことを目的とする。The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional art, and it prevents temporary malfunctions of the CPU from lasting forever, and when the CPU is unable to perform normal arithmetic processing on a regular basis, the control signal An object of the present invention is to provide a control device that facilitates the setting of safety by preventing the control from becoming a controlled object.
以下本発明の実施例を図−とともに説明する。Embodiments of the present invention will be described below with reference to the drawings.
第３図において、８はＯＲ手段４の出力を加えられるタ
イマで、タイマ８はＯＲ手段４の出力が問からｒＬＪに
反転したときにトリガされて’Ｌ （Ｔ＋ ＞ Ｔｏ
）秒間ｒＬＪ出力を行う再トリガ可能な単安定発振器を
含んで構成されている。又、ＣＰＵＩはＲｅ５ｅｔ 。In FIG. 3, 8 is a timer to which the output of the OR means 4 is added, and the timer 8 is triggered when the output of the OR means 4 is inverted from Q to rLJ.
) is comprised of a retriggerable monostable oscillator that outputs rLJ for seconds. Also, the CPUI is Re5et.
ｐｏｃ、ｐｏｗの各端子を有しておシ、ＡＮＤ手段６は
ＰＯＣ端子の出力とタイマ８の出力を入力される。It has terminals poc and pow, and the output of the POC terminal and the output of the timer 8 are input to the AND means 6.
他の構成は従来と同様である。The other configurations are the same as before.
次に上記装置の動作を第４図を用いて説明する。Next, the operation of the above device will be explained using FIG. 4.
まず、従来と同じく該装置に電源が印加されるとＦＯＲ
２は第４図←）に示すように一過性のｒＨＪ信号を出力
し、ＯＲ手段４を介してＲｅ５ｅｔ端子にｒＨＪ信号が
加わってＣＰＵＩは初期起動される。ＣＰＵＩは内蔵の
不揮発性記憶手段に予め定められた手順に従って演算処
理を行い、ＰＯＣ端子から制御信号を出力するとともに
ＰＯＷ端子から所定時間内にｒＨＪとｒＬＪが反転する
信号を出力する。又、ＷＤＴ３の時限Ｔ。秒はＰＯＷ端
子の出力の反転周期より長くしである。一方、タイマ８
はＯＲ手段４の出力がｒＨＪから「■７」に反転したと
きにトリガされ、１５秒後にｒＨＪとなるため、ＰＯＣ
端子からの制御信号はタイマ８の出力がｒＨＪとなって
はじめて制御対象５に加わる。ここで、ＣＰＵＩが一時
的な強電磁界等により誤動作してＰＯＷ端子の出力の反
転がなくなる４を介してＣＰＵＩは再起動され正規の演
算手順に復帰するため、強電磁界等がなくなると制御対
象５は正常に制御される。次にＣＰＵＩが故障等によシ
定常的に正規の演算処理ができない場合には、ＷＤＴ３
の出力によｆｉｃＰＵｌは再起動された後に、再びＣＰ
ＵＩはＴ。秒後にＷＤＴ３の出力により再起動されるが
、タイマ８はＣＰＵＩが再起動された後Ｔ、秒間はｒＬ
Ｊ出力であり、ｐｏｃ端子からの制御信号は制御対象５
にＴ１秒間は加わらない。しかも、Ｔ、 ＞ Ｔ。First, as in the past, when power is applied to the device, the FOR
2 outputs a transient rHJ signal as shown in FIG. The CPU performs arithmetic processing according to a predetermined procedure in a built-in nonvolatile storage means, outputs a control signal from the POC terminal, and outputs a signal that inverts rHJ and rLJ within a predetermined time from the POW terminal. Also, WDT3 time limit T. The second is longer than the inversion period of the output of the POW terminal. On the other hand, timer 8
is triggered when the output of OR means 4 is reversed from rHJ to "■7", and becomes rHJ after 15 seconds, so POC
The control signal from the terminal is applied to the controlled object 5 only after the output of the timer 8 becomes rHJ. Here, the CPU malfunctions due to a temporary strong electromagnetic field, etc., and the output of the POW terminal no longer inverts.The CPU is restarted via step 4 and returns to the normal calculation procedure, so when the strong electromagnetic field, etc. disappears, the controlled object 5 is normally controlled. Next, if the CPU is unable to regularly perform normal calculation processing due to a malfunction, etc., WDT3
After the output of ficPUl is restarted, it will restart the CP
UI is T. It is restarted by the output of WDT3 after a second, but the timer 8 is T after the CPUI is restarted, and the timer is rL for seconds.
J output, and the control signal from the poc terminal is the control target 5.
is not added for T1 seconds. Moreover, T, > T.
としているため、Ｔｏ秒間発生するＰＯＣ端子からの誤
制御信号は決して制御対象５に加わることがない。Therefore, the erroneous control signal from the POC terminal that occurs for To seconds is never applied to the controlled object 5.
以上のように本発明においては、ＣＰＵの一時的な誤動
作の場合には第１の時限装置によりこれを検出してＣＰ
Ｕを初期起動状態に復帰させておシ、誤動作の原因がな
くなれば直ちに正常状態に復帰する。又、第２の時限装
置の出力が生じることによ、りＣＰＵの制御信号は制御
対象に加わるが、第２の時限装置の時限は第１の時限装
置よシ長いので、一時的又は定常的にＣＰＵが誤動作し
ている場合には第２の時限装置には出力が生じず、誤動
作中のＣＰＵからの誤制御信号は制御対象には加わらな
い。As described above, in the present invention, in the case of a temporary malfunction of the CPU, the first timer detects this and the CPU
U is returned to its initial starting state, and if the cause of the malfunction is eliminated, it immediately returns to its normal state. Furthermore, when the output of the second timer is generated, the CPU control signal is applied to the controlled object, but since the time limit of the second timer is longer than that of the first timer, the output is temporarily or constantly. If the CPU is malfunctioning, no output is generated in the second timer, and the erroneous control signal from the malfunctioning CPU is not applied to the controlled object.
従って、制御対象のフェイルセイフの設定を容易に行う
ことができ、しかも簡単な構成で安価な制ａ装置が得ら
れる。Therefore, fail-safe settings for the controlled object can be easily performed, and an inexpensive a control device with a simple configuration can be obtained.
ｌ・・・中央処理装置、２・・・パワーオンリセット部
、３・・・ウォッチドッグタイマ部、４・・・ＯＲ手段
、５・・・制御対象、６・・・ＡＮＤ手段、８・・・タ
イマ。
尚、図中同一符号は同−又は相当部分を示す。
代理人 葛 野 信 −
牙１図
オ ２ 図
イ
ρｏｃ ｆｔ靜ゆＩ基若 ｆｔ、
” （定第３ｒＩ！Ｊ
第４図
ＰＯＣＦｌｌ： 隼’Ｉｆゴｐ
イｉ青ｔ手続補正書（自発〕
２、発明の名称
制御装置
３、補正をする者
名 称 （６０１）三菱電機株式会社代表者片山仁八
部
４、代理人
住 所 東京都千代田区丸の内二丁目２番３号５
、 補正の対象
明細書の発明の詳細な説明の欄。
６、 補正の内容
第３頁第１３行の「有する。」の後に「ここで、ｐｏｗ
はウォッチドッグタイマ用のポート出力、ＰＯＧはゲー
ト制御用のポート出力、ＰＯＣは制御用のポート出力端
子の略称である。」を加入する。
以 上l... Central processing unit, 2... Power-on reset section, 3... Watchdog timer section, 4... OR means, 5... Controlled object, 6... AND means, 8...・Timer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Fang 1 Figure 2 Figure I ρoc ft Seiyu I Motowaka ft,
” (Set 3rd rI!J 4th Figure POCFll: Hayabusa'If gop
Ai Blue T procedural amendment (spontaneous) 2. Name of the invention control device 3. Name of the person making the amendment (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent address 2 Marunouchi, Chiyoda-ku, Tokyo Chome 2-3-5
, Detailed description of the invention in the specification subject to amendment. 6. Contents of the amendment On page 3, line 13, after “has”, “here, pow
is a port output for watchdog timer, POG is an abbreviation for port output for gate control, and POC is an abbreviation for port output terminal for control. ” to join. that's all
Claims (1)
に応じた演算を行うとともに制御対象に対して制御信号
を出力しかつ正常動作時に正常動作信号を出力する中央
処理装置を備えた制御装置−において、電源印加時に出
力を出しこの出力を中央処理装置に加えて中央処理装置
を初期起動させる初期起動部と、前記正常動作信号が所
定時間とだえたことを検出しこの検出信号を中央処理装
置に加えて中央処理装置を初期起動させる第１の時限手
段と、初期起動部および第１の時限手段の出力を加えら
れるとともに第１の時限手段より時限が長い第２の時限
手段を備え、第２の時限手段に出力が生じたことを条件
として中央処理装置から制御対象に制御信号を加えるよ
うにしたことを特徴とする制御装置Ｗ０(1) A control device equipped with a central processing unit that performs calculations according to input conditions according to a procedure predetermined in a storage means, outputs a control signal to a controlled object, and outputs a normal operation signal during normal operation. an initial startup section that outputs an output when power is applied and adds this output to the central processing unit to initially start up the central processing unit; and an initial startup section that detects that the normal operation signal has stagnated for a predetermined time and sends this detection signal to the central processing unit. In addition, the central processing unit is provided with a first timer for initially starting the central processing unit, a second timer to which the outputs of the initial startup section and the first timer are added, and whose timer is longer than the first timer. A control device W0 characterized in that a control signal is applied from a central processing unit to a controlled object on the condition that an output is generated in a timer means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57114274A JPS593501A (en) | 1982-06-29 | 1982-06-29 | Control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57114274A JPS593501A (en) | 1982-06-29 | 1982-06-29 | Control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS593501A true JPS593501A (en) | 1984-01-10 |
Family
ID=14633714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57114274A Pending JPS593501A (en) | 1982-06-29 | 1982-06-29 | Control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS593501A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137301A (en) * | 1986-11-14 | 1988-06-09 | ローベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング | Monitoring of computer control-operator and monitoring circuit apparatus |
| JPH01113704U (en) * | 1988-01-26 | 1989-07-31 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5629741A (en) * | 1979-08-16 | 1981-03-25 | Mitsubishi Electric Corp | Undesired signal preventing circuit for programmable lsi |
| JPS5750004A (en) * | 1980-09-08 | 1982-03-24 | Honda Motor Co Ltd | Fault compensation device for electronic circuit |
-
1982
- 1982-06-29 JP JP57114274A patent/JPS593501A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5629741A (en) * | 1979-08-16 | 1981-03-25 | Mitsubishi Electric Corp | Undesired signal preventing circuit for programmable lsi |
| JPS5750004A (en) * | 1980-09-08 | 1982-03-24 | Honda Motor Co Ltd | Fault compensation device for electronic circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63137301A (en) * | 1986-11-14 | 1988-06-09 | ローベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング | Monitoring of computer control-operator and monitoring circuit apparatus |
| JPH01113704U (en) * | 1988-01-26 | 1989-07-31 |
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