JPS5934705A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5934705A
JPS5934705A JP57145042A JP14504282A JPS5934705A JP S5934705 A JPS5934705 A JP S5934705A JP 57145042 A JP57145042 A JP 57145042A JP 14504282 A JP14504282 A JP 14504282A JP S5934705 A JPS5934705 A JP S5934705A
Authority
JP
Japan
Prior art keywords
gain
fet
present
tier
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57145042A
Other languages
Japanese (ja)
Inventor
Masahiro Nishiuma
西馬 正博
Shutaro Nanbu
修太郎 南部
Shinichi Katsu
勝 新一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57145042A priority Critical patent/JPS5934705A/en
Publication of JPS5934705A publication Critical patent/JPS5934705A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To actuate a semiconductor IC with a low level of current, by cascading three tiers of FETs having small gate width and then applying a negative feedback to the gate of the 1st tier from the drain of the 3rd tier by a resistance. CONSTITUTION:A high-impedance connection is given between FET1 and 2 as well as FETs 2 and 3 with insertion of coupling capacitors 10 and 11 respectively. As a result, the gain of each FET increases. Furthermore the open loop gain can be increased more owing to the three-tier cascade. Thus the open loop gain is increased greatly up to about 60dB when the gate width of the FET is set at each value shown in a table. As a result, it is possible to increase the feedback resistance up to 8OMEGA to obtain the input/output matching. Thus, the overall gain can be increased up to about 30dB.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路に関する。本発明は3つの電界
効果トランジスタ(以下FETとよぶ)を結合コンデン
サにより直結し、かつ三段目から一段1」に抵抗を介し
て負帰還をかけることによな、高利得、低消費電力化を
i■能ならしめだFETモノリシック広帯域増幅器を提
供するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuits. The present invention achieves high gain and low power consumption by directly connecting three field effect transistors (hereinafter referred to as FETs) with a coupling capacitor and applying negative feedback from the third stage to the first stage through a resistor. The present invention provides an FET monolithic wideband amplifier with high performance.

従来例の構成とその問題点 FF、Tのドレイン・ゲート間に抵抗を挿入した負帰還
増幅器は、低雑音広帯域増幅器として公知である。しか
しながら、単一のFETを用いた負帰還増幅器では、た
とえば50〜1000M Hz +、y、’域で20d
B という大きな利、7Qをイ;するためKは、FET
のゲート幅を2間程度まで広げる心安がある。
Conventional configuration and its problems A negative feedback amplifier in which a resistor is inserted between the drain and gate of FF and T is known as a low noise wideband amplifier. However, in a negative feedback amplifier using a single FET, for example, 20d
In order to make a big profit of B, 7Q, K is FET
It is safe to widen the gate width to about 2 ken.

しかし、このようにすると人力容111が増大し、また
大きな動作電流が必要となる。
However, this increases the human power capacity 111 and requires a large operating current.

単−FETを用いた従来の負帰還増幅回路では、FET
のゲート幅を広げた場合でもオ ブ/ル−プ利得があま
り大きくとれない。例えばゲート幅1市のFETの場合
、オープンループ利得は約20dB である。従って、
人出力の整合をとるだめの帰還抵抗の値は約300Ωで
大きくとることができないため、全体の利得はさらに小
さくなる。壕だ、帰還抵抗が小さいためにNF(雑音指
数)も悪くなる。ゲート幅をさらに広げて相互コンダク
タンスgmを上げて、帰還抵抗を太きぐずれば、利得は
増大するが、動作電流が増大し、また、人力容量が増大
するために利得平坦性が悪くなり、帯域が狭くなる。
In a conventional negative feedback amplifier circuit using a single FET, the FET
Even if the gate width is widened, the ob/loop gain cannot be increased very much. For example, in the case of an FET with a gate width of 1 inch, the open loop gain is about 20 dB. Therefore,
The value of the feedback resistor for matching the human output is about 300Ω, and cannot be made large, so the overall gain becomes even smaller. It's a trench, and the return resistance is small, so the NF (noise figure) is also bad. If the gate width is further widened, the transconductance gm is increased, and the feedback resistor is made thicker, the gain will increase, but the operating current will increase, and the gain flatness will worsen due to the increase in human power capacitance. becomes narrower.

発明の1」的 本発明は上記従来の欠点を除去するものであり、低電流
で動作する高利イ()広帯域増幅器の半導体集積回路を
提供することを目的とする。
A first aspect of the present invention is to eliminate the above-mentioned drawbacks of the conventional art, and an object of the present invention is to provide a semiconductor integrated circuit of a high gain broadband amplifier that operates with low current.

発明の構成 本発明は、ゲート幅の小さいFETを三段縦続接続し、
三段目のドレインから初段のゲー トに抵抗により負帰
還をかけることにより、低電流で動作する高利イ()広
帯域増幅器を−iJ能ならしめるものである。
Structure of the Invention The present invention connects FETs with small gate widths in three stages,
By applying negative feedback from the drain of the third stage to the gate of the first stage using a resistor, a high gain broadband amplifier that operates with low current can be made to have -iJ performance.

実施例の説明 以下、実施例に基ついて本発明を説明する。Description of examples Hereinafter, the present invention will be explained based on Examples.

第1図は、本発明の実施例の半導体集積回路の回路図で
ある。1,2.3は、それぞれGaAsFET、4は入
力端子、6は出力端子である。
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention. 1, 2.3 are GaAsFETs, 4 is an input terminal, and 6 is an output terminal.

6.7はドレインバイアス端子、8.9はゲートバイア
ス端子、10.11は結合コンデンサである。12.1
3はそれぞれ帰還容量・帰還抵抗である。
6.7 is a drain bias terminal, 8.9 is a gate bias terminal, and 10.11 is a coupling capacitor. 12.1
3 are a feedback capacitance and a feedback resistance, respectively.

同回路では、各FET1と2.2と3間はそれぞれ結合
コンデンサ10,11のみを挿入した高インピーダンス
結合となっているために、各FETの利得は大きく、ま
た三段接続のだめにオ シンループ利得はさらに大きく
できる。本発明の実施例で用いたFETのゲート幅は、
FET1で400μm、FET2および3で200μm
である。
In this circuit, only coupling capacitors 10 and 11 are inserted between FETs 1, 2, and 3, respectively, for high impedance coupling, so the gain of each FET is large, and the oscilloscope loop gain is large due to the three-stage connection. can be made even larger. The gate width of the FET used in the example of the present invention is
400μm for FET1, 200μm for FET2 and 3
It is.

次表に本実施例の各要素の値を示す。The following table shows the values of each element in this example.

表 この場合オープンループ利得は約60dB と非常に大
きくできる。従って、入出力の整合をとるための帰還抵
抗も8#Ωと犬きくできだ。このだめに、全体の利得は
約30dBと大きくなる。
In this case, the open loop gain can be as large as approximately 60 dB. Therefore, the feedback resistance for input/output matching is also very high at 8Ω. As a result, the overall gain increases to about 30 dB.

第2図、第3図は単−FETを用いた負帰還増幅回路と
本発明の実施例の増幅回路のSパラメータの割算結果を
比較して示したものである。14は本発明の実施例の増
幅回路のls211、の特性曲線、15は単−FETに
よる負帰還増幅回路のめ l S 211の特性曲線である。特性曲線14より4
.アかるように低周波側で1s2iの値が小さくなって
いるのは、各FET間に挿入した結合コンデンサの影響
によるが、l5211の平坦性は良くなっている。
FIGS. 2 and 3 compare and show the results of dividing the S parameters of a negative feedback amplifier circuit using a single FET and an amplifier circuit according to an embodiment of the present invention. 14 is a characteristic curve of ls211 of the amplifier circuit according to the embodiment of the present invention, and 15 is a characteristic curve of ls211 of a negative feedback amplifier circuit using a single FET. 4 from characteristic curve 14
.. The reason why the value of 1s2i is small on the low frequency side as shown in the figure is due to the influence of the coupling capacitor inserted between each FET, but the flatness of 15211 is improved.

第3図において、16および17はそれぞれ単−FET
による負帰還増幅回路のI S 221の特性曲線を、
18および19はそれぞれ本発明の実施例の増幅回路の
ls++lおよびl S 221の特性曲線をそれぞれ
示す。
In FIG. 3, 16 and 17 are single-FETs, respectively.
The characteristic curve of IS 221 of the negative feedback amplifier circuit according to
18 and 19 indicate the characteristic curves of ls++l and ls221, respectively, of the amplifier circuit of the embodiment of the present invention.

さらに第4図はこの回路を用いたGaAsモノリミック
IC広帯域増幅器の利得およびNFの周波数特性を示す
Further, FIG. 4 shows the gain and NF frequency characteristics of a GaAs monolithic IC broadband amplifier using this circuit.

同図において、20は利得の周波数特性の曲線を、21
はNFの周波数特性の曲線をそれぞれ示す。
In the figure, 20 represents the gain frequency characteristic curve, and 21
respectively show the curves of the frequency characteristics of the NF.

各素子の値は前夫で示したものと同じである。The values of each element are the same as those shown in the previous example.

第4図に示すように60〜100100O帯域で約28
 dBの平坦な利得特性が得られている。
Approximately 28 in the 60-100100O band as shown in Figure 4
A flat gain characteristic of dB is obtained.

一方、NFは、帰還抵抗が大きいために50〜1000
 MHz 帯域で2.3 d B以下の1「1が得られ
ている。ドレイン電圧は3vで、動作電流は25mAで
あり、ゲート幅1o00μmの午−FETによる従来の
増幅器の動作電流30mAに比べて、約20%減少して
いる。なお、以上実施例の説明では帰還容量を挿入した
場合で説明したが、この帰還容量は挿入しなくてもよい
。まだ、」二配実施例では、各段のFETのゲート幅と
しては400μm。
On the other hand, NF has a high feedback resistance of 50 to 1000
1'1 of less than 2.3 dB has been obtained in the MHz band.The drain voltage is 3V and the operating current is 25mA, compared to the operating current of 30mA in a conventional amplifier using an FET with a gate width of 100μm. , is reduced by about 20%. In the above embodiment, the case where a feedback capacitor is inserted has been explained, but this feedback capacitor does not need to be inserted. The gate width of the FET is 400 μm.

200μm、200μmの場合で説明しだが、低歪特性
を持たせるのに、各段のFETのゲート幅を100μm
、200μm、300μmとした構成においても同様の
効果が期待できる。
I explained the case of 200μm, 200μm, but in order to have low distortion characteristics, the gate width of each stage FET is 100μm.
, 200 μm, and 300 μm, similar effects can be expected.

発明の効果 以上述べたように、本発明の半導体集積回路はFETを
三段、結合コンデンサにより直結し、三段目のドレイン
から一段目のゲートに抵抗により負帰還をかけることに
より、消費電力の小さな゛高利得低雑音広帯域増幅器の
作製を可能にするものであり、工業上の利用価値が高い
Effects of the Invention As described above, the semiconductor integrated circuit of the present invention reduces power consumption by directly connecting three stages of FETs through coupling capacitors and applying negative feedback from the drain of the third stage to the gate of the first stage using a resistor. This makes it possible to produce a small, high-gain, low-noise, wideband amplifier, and has high industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例における半導体集積回路の回路
図、第2図、第3図は本発明の実施例の回路および従来
の単−FETによる負帰還増幅回路のSパラメータの計
算結果を示す図、第4図は本発明の実姉例の回路におけ
る利得およびNFの周波数特性を示す図です。 1・・・・・・初段FET、2・・・・・・二段目FE
T、3・・・・・・三段IJ F E T、4・・・・
・・入力端子、5・・・・・出力端子、6.7・・・・
・トレインバイアス端子、8 、9・・・・・ケートバ
イアス端子、10.11・山・・結合コンデンサ、12
・・・・・・帰還容量、13・・・・・・帰還抵抗、1
4・・・・・・本発明回路の1s211の計算結果、1
5・・・・・・単−FETによる負帰還回路の1s21
1の計算結果の曲線、16.17  ・・・・単−FE
Tによる負帰還回路のls++l 、1s221 の計
算結果の曲線、18.19・・・・本実施例の回路の1
8111,1s771の計算結果の曲線、20 ・・本
発明の実施例の回路の利得の周波数特性の曲線、21・
・・・同回路のNFの周波数特性の曲線。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 朋償数(MHir) 第3図 晶:J爽秋CNHz) 第4図 M 5灰1矢(hjHi)
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are calculation results of S parameters of a circuit according to an embodiment of the present invention and a conventional negative feedback amplifier circuit using a single FET. The figure shown in Figure 4 is a diagram showing the gain and NF frequency characteristics of a circuit according to an actual sister example of the present invention. 1...First stage FET, 2...Second stage FE
T, 3...Three stages IJ F E T, 4...
...Input terminal, 5...Output terminal, 6.7...
・Train bias terminal, 8, 9...Kate bias terminal, 10.11・Mountain...Coupling capacitor, 12
...Feedback capacitance, 13...Feedback resistance, 1
4... Calculation result of 1s211 of the circuit of the present invention, 1
5...1s21 of negative feedback circuit using single-FET
1 calculation result curve, 16.17 ... Single-FE
Curve of the calculation result of ls++l, 1s221 of the negative feedback circuit by T, 18.19... 1 of the circuit of this example
8111, 1s771 calculation result curve, 20...Curve of the frequency characteristic of the gain of the circuit of the embodiment of the present invention, 21.
...Curve of frequency characteristics of NF of the same circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2: MHir Figure 3: J Soju CNHz Figure 4: M 5 gray 1 arrow (hjHi)

Claims (2)

【特許請求の範囲】[Claims] (1)  三個の電界効果トランジスタを結合コンデン
サを介して三段結合し、三段1」の電界効果トランジス
タのドレインと初段の電界効果トランジスタのゲート間
に抵抗を挿入することを特徴とする半導体集積回路。
(1) A semiconductor characterized in that three field effect transistors are coupled in three stages via a coupling capacitor, and a resistor is inserted between the drain of the field effect transistor in the third stage and the gate of the first stage field effect transistor. integrated circuit.
(2)抵抗と直列に容置を挿入することを特徴とする特
許請求の範囲第1項記載の半導体集積回路。
(2) The semiconductor integrated circuit according to claim 1, wherein a container is inserted in series with the resistor.
JP57145042A 1982-08-20 1982-08-20 Semiconductor integrated circuit Pending JPS5934705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57145042A JPS5934705A (en) 1982-08-20 1982-08-20 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57145042A JPS5934705A (en) 1982-08-20 1982-08-20 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5934705A true JPS5934705A (en) 1984-02-25

Family

ID=15376042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57145042A Pending JPS5934705A (en) 1982-08-20 1982-08-20 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5934705A (en)

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