JPS6096906A - Gaas fet circuit - Google Patents

Abstract

PURPOSE:To obtain excellent high-frequency characteristics and balancing characteristics by connecting a source electrode of the 3rd FET to a common connecting point of source electrodes of two FETs and connecting its gate to a high-frequency signal input terminal. CONSTITUTION:An FET48 is provided to correct the loss of a high-frequency current flowed to the source of an FET47. The presence of the FET48 allows the input high-frequency signal fed to a terminal 6 to be fed to the gate of an FET46 and also to the gate of the FET48 to correct the high-frequency current flowed to a resistor 21. As a result, the high-frequency current flowed to the source and drain of the FET47 is increased and the level of output terminals 7 and 8 is arranged. Thus, an unbalance/balance exchange circuit with excellent high-frequency characteristics and well-balanced output levels is realized on a GaAs wafer by utilizing the high-speed property of a GaAs FET.

Description

[Detailed description of the invention] The present invention is a GaAs semiconductor wafer-type KFET.

QaAs FET ICs, more specifically those I
This invention relates to a GaAs FET IC circuit that converts an unbalanced high frequency signal into a balanced high frequency signal.

Conventionally, ICs made by forming FETs and resistors on GaAs wafers have mainly been amplifiers and mixers, and there are few examples of ICs that generate balanced signals internally.

On the other hand, ICs using a silicon bipolar process generally use differential transistor circuits to perform unbalanced/balanced conversion, but in this case, the frequency characteristics are not good and operation up to several hundred MHz is not possible. It has become a limit.

FIG. 1 shows an example of an unbalance/balance conversion circuit using a silicon bipolar process.

In the figure, 4o and 41 are differential transistors, and 42 is a constant current transistor. In this circuit, when a single unbalanced signal is applied to the input terminal 1, a balanced signal with a uniform level is obtained from the output terminals 2 and 6, but the frequency thereof is limited to a relatively low frequency.

FIG. 2 shows a conventional example of an unbalance/balance conversion circuit fabricated on a GaAs wafer based on the same idea as in FIG. 1.

In this figure, by applying a power supply voltage to terminal 4 and inputting a high frequency signal through terminal 1, a high frequency differential signal can be obtained at terminals 2 and 6. The characteristics of this circuit are that the gain is almost constant over high frequencies exceeding IGHz, and the phase difference between both outputs is approximately 180 degrees.However, there is a gain difference between both outputs, and the output 6 side There was a drawback that the gain of 1 was lowered by several d13.

The object of the present invention is to provide a Q
Unbalance using aAs wafer.

An object of the present invention is to provide a balance conversion IC circuit.

GaAsFET according to the present invention to achieve the above object
In the circuit, a FET and a resistor are formed on the same GaAs wafer, and the source electrodes of the first and 20th FETs are connected directly or through a resistor after connecting a resistor with the same resistance value to each source electrode and then common connection. and connect it to the ground terminal.
A terminal to which the source electrode of the third FET is connected directly or through a resistor to the common connection point, the gate electrode of the third FET is connected to the gate electrode of the first FET, and a high frequency signal is input. and further connect to the 20th floor.
The gate electrode of the ET is grounded at high frequency or connected to an electrode for grounding at high frequency outside the wafer, and the drain electrodes of the first and second FETs are connected to another circuit that receives the output of this IC circuit. to the power supply terminal through the resistor, or to the power supply terminal and the output terminal respectively through the resistor.
Alternatively, they can be configured by connecting each to an output terminal.

According to the above structure, the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 8 is a circuit diagram showing a first embodiment of a GaAs FITIC circuit according to the present invention. In order to explain the operation of this embodiment, the operation in the case where the third FET 48 is not present will be explained first, and then the FET according to the present invention will be explained.
The function of 48 will be explained. The example of Party B is the first and second
In this case, the source electrodes of the 0FETs are directly connected, and the respective drain electrodes are connected to the power supply terminal 2 through the resistors 22 and 25, respectively, and are also connected to the output terminals 7 and 8, respectively. °ru An unbalanced high frequency signal is applied between input terminal 6 and ground. GaA
An opposite phase signal is output to the output terminal 7 by the operation of the first FET 46 formed on the S wafer. In addition, when the input signal frequency changes, the signal level of one output remains approximately constant over the higher frequency GaAa
This is a feature when using FET. A high frequency current flows through the resistor 22 and the same high frequency current flows through the resistor 21 as a result of which an output is obtained at the terminal 7. This current path and the second path made on the other GaAs wafer.
As long as the path through which the source current of the second FET 47 flows is considered to be the same, the gate of the second FET 47 is grounded at high frequency via the capacitor 6.
The same high-frequency current flows through the drain resistor 26 of 47, and the direction of the current flow is opposite to that of the resistor 22, so the level between output terminals 7 and 8 is the same with respect to ground, and the polarity is also the same. It is possible to obtain a balanced signal with a 180 degree difference.

The above explanation should also hold true for the unbalanced/balanced conversion circuit (Fig. 2) on a GaAs wafer, which is an application of the conventional silicon bipolar IC embodiment.
According to the above consideration, even in the circuit shown in Fig. 2, the output terminal 2
and 6, the level between ground and ground is the same, and the polarity is 1.
It should be possible to obtain a balanced signal with an 80 degree difference. However, in reality, the signal level obtained at terminal 8 is several dB lower than the signal level obtained at terminal 7, and this holds true even in a sufficiently low frequency band. The cause of this is Q a
This is believed to be because the path of current through the source of FET 450 on the A8 wafer and the path of current through the source of FET 44 are actually the same and strong.

FIG. 4 shows an equivalent circuit diagram of the circuit surrounding the sources of FETs 46 and 44 in the circuit of FIG. 2, and will be discussed.

In the figure, resistance 25 indicates the source resistance existing inside FFI; Ta2, and 49 indicates the ideal FET excluding the source resistance.
shows. Similarly, the resistor 26 is the internal source resistance of the FET 44, and the reference numeral 50 indicates an ideal FET except for this. FET
The circuit consisting of the resistor 45 and the resistor 18 is regarded as a resistor whose value is constant at high frequencies, and its equivalent resistance is represented by the resistor 24. GaA
Due to the presence of the source resistance 25.26 formed on the s wafer and present inside the nine FETs 45.44, the ideal FET 4
The path of the source current of 9.50 is not exactly the same, and the current applied to the source of the ideal FET 50 is resistor 25.2.
6 to reduce the partial pressure.

Based on the above considerations! >FE made on GaAs wafer
Reduce the source resistance present inside T or FE
'l', 45. It is considered that if the circuit consisting of the resistor 18 functions perfectly as a constant current circuit and the value of the equivalent resistor 24 is made sufficiently large, the output levels of the output terminals 2.5 can be made almost the same. FE fabricated on GaAs wafer
The source resistance inside 'T is determined by the structure of the FET and is not affected by changes in the circuit. Also, GaA
A constant current circuit using a FET does not function as a sufficiently effective constant current source because the Gm of the FET is not large.
To compensate for the loss of high frequency current flowing into the source of
A new third FET 4B is prepared. FET with
Due to the existence of
The high frequency current applied to the gate of ET 48 and flowing through resistor 21 is corrected, the high frequency current flowing through the source and drain of second FET 47 increases, and the levels of output terminals 7 and 8 can be made equal. In Fig. 3, resistors 19 and 20 are used as gate biases and are connected to the same bias supply terminal 5, but this can also be biased individually using the power supply voltage and ground applied to terminal 9. .

Further, by adjusting the voltage applied to the bias supply terminal 5, the operating point of the FET can be changed and the balance of the circuit can be optimized. In addition, in order to further improve the high frequency characteristics, the first and second FETs 46, 47
It is also possible to insert a resistor in series with the source. However, in that case, the value of the resistor 21 must be chosen large in order to maintain balance, and the current consumption by the resistor 21 must be allowed. Although this embodiment shows an example in which an output is obtained from the output terminal 7.8, this signal can also be directly connected to the same chip or to another circuit for integration. Furthermore, the input side can also be connected to other circuits within the same chip to achieve integration. The capacitor 66 for grounding the gate of the second FET 47 at high frequencies may be a separate component outside the chip, or may operate only at high frequencies. Similarly, the capacitor 32 can also be attached externally or offset on the chip.

FIG. 5 shows another embodiment of the invention.

In this embodiment, resistors 27 and 28 are inserted in series with the source and drain of the third FET4B, and the
The voltage of the gate of 0FET46 and 48 is determined by the voltage division of resistors 35 and
The gate bias of 7 is different from the embodiment of FIG. Other configurations are the same as in Figure 3.

From the above, according to the present invention, the high-speed characteristics of GaAs FETs are utilized to provide an unbalanced device with excellent high frequency characteristics and a well-balanced output level.

A balanced conversion circuit can be realized on a GaAs wafer.

The circuit according to the present invention improves the clamping characteristics.

It is effective due to its small size and low cost.

[Brief explanation of the drawing]

Figure 1 shows a conventional unbalanced/balanced conversion IC circuit using a silicon bipolar process.A conventional unbalanced/balanced conversion IC circuit formed on a QaAs wafer
FIG. 3 is a circuit diagram showing the circuit. FIG. 5 is a circuit diagram showing the first and second embodiments of the GaAs FET circuit according to the present invention, and FIG. 4 is an equivalent circuit diagram showing the vicinity of the source of the differential circuit in the circuit of FIG. 1.6...Input terminal 2.7...Negative phase output terminal 6.8...In-phase output terminal 4.9...Power supply terminal 5...Bias supply terminal 10~24.27~ 29.54~66...Resistance 30.32...Fist input DC cut capacitor 31.3
3...High-frequency grounding capacitor 40-42...Silicon bipolar transistor 46-50...IIGaAB FET Patent applicant NEC Corporation representative Patent attorney Inoro Inoro Series 1 Figure 2 Figure 2 3 Figure 3 Figure 4, Figure 5vA Procedural Amendment January 298, 1985 Patent Application No. 204459 of 1988 2, Title of Invention GaAs FET Circuit 3, Relationship with the Amendment Person Case Patent Applicant 4, Agent Hitoshi Ichio Noucheba Special Application 1984-204.459>+1)
The scope of claims is amended as follows. [2. Claims FET and resistor are formed on the same -Qa, As wafer, and the source electrodes of the first and second FETs are directly connected or the respective source electrodes have the same resistance value) Connect the fault point to i to the ground terminal via a resistor, connect the source electrode of the third FET to the common connection point directly or via a resistor, Furthermore, a third FET
Connect the gate electrode of the first FET to the gate electrode of the first FET and connect it to a terminal for inputting a high frequency signal, and further ground the gate electrode of the second FET to the high frequency 0 dimension,
Or contact with high frequency outside the wafer! ! Sumeta no W
Connect the drain electrodes of the first and second FETs to the power supply terminal through another circuit that receives the output of this IC circuit, and then connect the drain electrodes of the first and second FETs to the power supply terminal through a resistor. A GaAs FE, 7 circuits, characterized in that they are connected to a power supply terminal and each output terminal, or to each output terminal (2) from page 3, line 20 of Book Ill. The phrase "In order to achieve the above object..." in Section 1 of Section □ of the same document is amended as follows: [In order to achieve the above object, the GaAs
In the FET circuit, the FET and the resistor are formed on the same 〇aAs wafer, and the source electrodes of the first and second FETs are connected directly to each other.
Alternatively, connect a resistor equal to the resistance value in series to each source electrode, then connect them in common, connect the common connection point to the ground terminal through the resistor, and connect the source electrode of the third FET directly or through the resistor. The gate electrode of the third FET is connected to the common connection point, the gate electrode of the third FET is connected to the gate electrode of the first FET, and the gate electrode of the second FET is connected to the terminal for inputting a high frequency signal. Connect the drain electrodes of the first and second FETs via another circuit that is grounded at high frequency or connected to an electrode for grounding at high frequency outside the wafer, and which receives the output of this IC circuit. They are configured to be connected to a power supply terminal, or to a power supply terminal and an output terminal, respectively, or to a cutting edge terminal, respectively, via a resistor. (3) "Terminal 2" on page 5, line 9 of the specification is corrected to "terminal 9." (4) Delete "made on other GaAs wafers" from page 5, line 20 to page 6, line 1 of the specification. (5) ``Terminal 8'' on page 6, line 17 of the specification is 1 terminal 3''
Correct to. (6) “Terminal 7” on page 6, line 17 to line 18 of the specification
" is corrected to "terminal 2". (7) [Resistors 25, 26J] on page 7, line 17 of the specification
Correct the resistance to 25, 24J. (8) Add the following after "...does not serve as a constant current source" on page 8, line 9 of the specification. "In addition, at high frequencies, the effect of increasing the value of the equivalent resistance 24 is small unless the distributed capacitance is reduced." (9) "Can be" on page 9, line 6 of the specification is changed to " It is highly effective in monolithic ICs because it can 00) "Current consumption" on page 9, line 11 of the specification is corrected to "voltage consumption." (11) "Circuit inside the chip or other circuits" on page 9, line 14 of the specification is corrected to "circuit inside the chip." (12) "Anything on the chip" in the second line of page 10 of the specification should be corrected to "anything on the chip." (13) "10-24" on page 11, line 12 of the specification is corrected to "10-26". that's all

Claims (1)

[Claims] A FET and a resistor are formed on the same GaAB wafer, and the first
and - Connect the source electrode of the second FET directly, or connect a resistor with the same resistance to each source electrode, make a common connection, and then connect it to the ground terminal via the resistor, and connect the source electrode of the third FET to the ground terminal. The gate electrode of the third FET is connected to the common connection point directly or through a resistor, and the gate electrode of the third FET is connected to the gate electrode of the first FET, and also connected to the terminal for inputting a high frequency signal. FET of
The gate electrode of the FET is grounded at high frequency or connected to an electrode for grounding at high frequency outside the wafer, and the drain electrodes of the first and second FETs are connected to another circuit that receives the output of this IC circuit. 1. A GaAs FET circuit characterized in that the GaAs FET circuit is configured such that the GaAs FET circuit is connected to a power supply terminal through a resistor, or to a power supply terminal and an output terminal through a resistor, respectively, or to an output terminal.