JPS5934023B2 - receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an FM receiver using a phase-locked loop (hereinafter abbreviated as PLL), and particularly to an FM stereo demodulation circuit suitable for a semiconductor integrated circuit.

First, the operating principle of a stereo demodulation circuit using a PLL circuit shown in FIG. 1 will be explained according to a system block diagram thereof.

In Figure 1, the P that reproduces the 38KHz subcarrier
The LL circuit is composed of a phase detector 1, a low-pass film 2, a DC amplifier 3, a voltage controlled oscillator 4, a 1/2 frequency divider circuit 5 in the first stage, and a 1/2 frequency divider circuit 6 in the second stage. ing.

The output frequency of the voltage controlled oscillator 4 is 76 KHz, and this signal passes through the 1/2 divider circuits 5 and 6 to have a frequency of 19 KHz and returns to the phase detector 1.

This phase detector 1 receives 19KHz from the 1/2 frequency divider circuit 6.
The signal and the input signal are phase detected.

Therefore, if the input signal contains a 19KHz pint signal, the output of the phase detector 1 is the output of the low-pass filter 2.
A DC voltage component is generated.

This DC voltage component is amplified by a DC amplifier 3 and then used as a control signal for a voltage controlled oscillator 4.

As a result, the voltage controlled oscillator 4 is phase-locked to the pilot signal of the input signal, and the 38
The KHz output signal can accurately maintain the correct phase for demodulating stereo signals.

Next, the circuit related to the stereo switch is the phase detector 7,
It consists of a low-pass filter 8, a Schmitt trigger circuit 9, stereo switches 10 and 11, and a stereo display lamp 12 connected to the stereo switch 11.

In the current state where phase lock is applied, the input pilot signal and the reproduced 19 KHz signal are out of phase by 90°.

Therefore, the first-stage 1/2 frequency divider 5 is provided with a 1/2 frequency divider 1 that can obtain 19 KHz that is in phase with the pilot signal.
3 is connected and this 19 Kl (Z output is added to the phase detector 7 for operating the stereo switch 10.11. When the input signal is phase detected, the DC voltage component proportional to the intensity of the input pilot signal is passed through the low-pass filter. It is taken out at 8.

This DC voltage component drives the Schmitt trigger circuit at the next stage, operating the stereo switch 10, and turning on the stereo switch 11 to light the stereo display lamp 12.

14 is a preamplifier, 15 is an input signal and a regenerated 38
A stereo demodulator to which a KHz subcarrier is added.

Since such a PLL demodulation circuit does not require inductance, it is suitable for use as a semiconductor integrated circuit.
When used in an M, FM stereo receiver, the intensity of the input pilot signal is detected by the phase detector 7 and the low-pass filter 8 during FM reception, and the stereo switch 1
In addition to operating the stereo demodulators 0 and 11, it is necessary to forcibly switch the stereo demodulator to monaural operation during the muting operation using a muting signal that detects the input electric field strength at the FMIP amplification stage.

Also, when receiving AM, the oscillation output of voltage controlled oscillator 4 is AM
Voltage controlled oscillator 4 because it interferes with the tuner.
It is necessary to stop the oscillation operation of the

In the conventional PLL stereo demodulation IC, the voltage controlled oscillator 4
Stopping the oscillation operation and forcing monaural switching can be done from outside the IC.
This function was performed using separate terminals.

The method is shown in FIGS. 2 and 3.

The same parts as in FIG. 1 are given the same reference numerals.

FIG. 2 shows the circuit configuration of the voltage controlled oscillator 4 in FIG.
It is made up of.

In FIG. 2, when the oscillation operation of the voltage controlled oscillator 4 is stopped, a changeover switch 19 is installed in series with the timing circuit 17 connected to the terminal 18, and when AM reception is performed, the timing circuit 17 is disconnected to stop the oscillation operation of the voltage controlled oscillator 4.

FIG. 3 shows the circuit configuration of the low-pass filter 8 in FIG. 1, and the low-pass filter 8 is configured together with a DC amplifier 20.

When forced monaural switching is performed in Figure 3,
The collector of the switching transistor 23 is connected to the external terminal 21 which is the input of the DC amplifier 20 configured as a differential, and the muting signal from the FMIF amplification stage is applied to the base to make the transistor 23 conductive. During this time, a DC voltage is generated to drive the Schmitt trigger circuit 9 by 1.

Similarly, a DC voltage is applied to the base of the transistor 23 to make the signal into a monaural state by switching the selector switch.

As mentioned above, in the conventional PLL stereo demodulation circuit, when it is integrated, a changeover switch and a transistor are connected externally, but the use of transistors naturally leads to an increase in cost, and the wiring from the timing circuit 17 to the selector switch is , stray capacitance, and dielectrics have an adverse effect on the timing circuit, which has been a problem in the design of stereo receivers.

In view of the above-mentioned problems, the present invention has been developed so that the switch function for stopping the oscillation operation of the voltage controlled oscillator 4 and the switch function for performing forced monaural switching can be operated by the same control signal, and when integrated circuits are provided. A PLL stereo demodulation circuit that can control the oscillation operation stop of a voltage controlled oscillator and forced monaural switching by the DC voltage level applied to one electrode terminal, and incorporates the above two switch functions while minimizing the increase in the number of integrated circuit terminals. We aim to provide the following.

FIG. 4 is a block diagram for explaining the present invention.
In contrast to this figure and FIG. 3, the same parts are given the same reference numerals.

The first switch circuit 24 connected to the Schmitt trigger circuit 9 operates when the DC voltage applied to the input terminal 26 reaches the first switch voltage, and the stereo switches 10 and 11
the stereo demodulator to monaural operation, and the stereo indicator lamp is turned off.

In this case, the first switch circuit 24 may drive the Schmitt trigger circuit 9 or the stereo switches 10 and 1.
1 may be directly driven.

The second switch circuit 25 connected to the oscillation circuit 16 operates when the potential of the input terminal 26 reaches the second switch voltage and stops the oscillation circuit 16 from oscillating.

For example, when the first switch circuit 24 is operated at a level higher than the first switch voltage, the second switch voltage is set to a higher potential than the first switch voltage, and the second switch circuit 24 is operated at a higher level than the first switch voltage. is configured to operate at or above the switch voltage of

Therefore, when a voltage higher than the second switch voltage is applied to the terminal 26, the first switch circuit 24 and the second switch circuit 25 operate simultaneously, the stereo demodulator switches to forced monaural, and the voltage controlled oscillator stops oscillating. become a state.

Normally, the oscillation of the voltage controlled oscillator is stopped only when receiving AM broadcasts or when reproducing FM broadcasts in monaural, so the operation of the first and second switch circuits described above poses no problems compared to the conventional system. It is possible to use two functions depending on the voltage applied to one terminal without causing any problem.

FIG. 5 shows a circuit configuration of an embodiment according to the present invention, and in contrast to FIG. 4, corresponding parts are given the same reference numerals.

31 is a positive DC voltage when forced monaural switching is required in a voltage generation circuit such as a muting voltage generation circuit in the FMIF stage.
Generates voltage.

Reference numeral 32 denotes a selector switch for AM reception. During AM reception, the DC voltage from the voltage generation circuit 31 is applied to the base of the transistor 27 via the resistor at the input terminal 26.
(2) When the collector current of the transistor 27 is reached, the first switch circuit 24 including the transistor 27
operates and forced monaural switching is performed.

The transistors 28 and 29 constitute a differential amplifier, and the base of the transistor 29 is supplied with a bias voltage of about 6 cm from a voltage source 30, so that the potential of the input terminal 26 is equal to the voltage source 30.
, transistor 28 is non-conducting.

Turn on the selector switch 32 and connect the voltage source 30 to the input terminal.
When a voltage sufficiently higher than the voltage of , for example, a power supply voltage of 12 V is applied, the transistor 28 becomes conductive, and its collector current operates the second switch circuit 25 including the transistors 2 B and -29 to stop the voltage controlled oscillator.

Moreover, according to the configuration shown in FIG.
This reduces power consumption when the switch circuit operates, and prevents shock noise from occurring from the speaker.

That is, since two diodes are connected between the base of the transistor 27 in the first switch circuit 24 and the ground, the current that flows when the transistor 27 is turned on is equal to the emitter resistance of the transistor 27 and one diode. This current remains constant even if the voltage at the input terminal 26 is amplified.

By closing the selector switch 32, the voltage source 3 at the terminal 26 is
When it becomes larger than 0, the transistor 28 becomes conductive, but
The transistors 28 and 29 constitute a differential amplifier circuit, and the current flowing through the circuit is constant due to the constant current source provided between the common emitter connection point of the transistors 28 and 29 and the ground. The current flowing through the transistor 28 is constant regardless of the voltage at the terminal 26 of 30 or more.

In this way, even when transistors 27 and 28 are conductive, the current flowing through them is constant and does not increase as the voltage at terminal 26 increases.

Therefore, even if sufficient voltage is supplied to terminal 26 to make transistors 27 and 28 conductive, the voltage consumed by their conduction is suppressed.

The fact that only a constant current flows through the transistors 27 and 28 even when a sufficiently high voltage is applied to the terminal 26 means that the current change caused by conduction of these transistors 27 and 28 is small.

Smaller current changes also result in smaller voltage fluctuations, thereby preventing pops from a speaker coupled to the output of the receiver.

When a large voltage fluctuation occurs due to the switching operation of the switch circuit, the fluctuation is fed back to the input of an amplifier, for example, and causes a large output voltage fluctuation, resulting in a popping sound from the speaker.

As described above, the receiver according to the present invention not only can stop the oscillation operation of the voltage controlled oscillator for AM passive and switch to forced monaural operation from a common input terminal, but also can reduce the power consumption that may be caused by these switching operations. The problems of increase and pop noise generation are also solved at the same time.

Note that the second switch circuit 25 is a differential transistor 28
．． Instead of 29, a plurality of diodes may be inserted between the base of the transistor 28 and the ground as in the first switch circuit 24.

However, since the first and second switch circuits 24 and 25 require a large difference in threshold voltage, the number of diodes required increases.

Since the diode and the transistor require the same area in an integrated circuit, it is advantageous for the second switch circuit 25 to have a differential configuration as in the present invention.

The voltage generation circuit 31 is set to a voltage that is output in a range lower than the voltage of the voltage source 30, and the selector switch 32 is set to output a voltage in a range lower than the voltage of the voltage source 30, and the selector switch 32 is set to the input terminal 2 if a voltage higher than the voltage of the voltage source 30 is supplied.
6 can be used to easily realize two operations: forced monaural switching of the FM stereo demodulation IC and stopping of oscillation of the voltage controlled oscillator.

[Brief explanation of drawings]

Figure 1 is a system block diagram of a stereo demodulation circuit using a PLL circuit, Figure 2 is a circuit diagram showing a conventional example of a voltage controlled oscillator with an oscillation stop function, and Figure 3 is a conventional example with a forced monaural switching function. FIG. 4 is a functional block diagram showing an embodiment of the present invention, and FIG. 5 is a circuit connection diagram showing a specific embodiment of the present invention. 16...Oscillation circuit, 17...Timing circuit, 1B, 21.22, 26...Terminal, 1
9, 32...Choice switch, 20...
DC amplifier, 23...transistor switch,
24... Forced monaural changeover switch circuit, 25
・・・・・・Oscillation stop switch circuit, 27.28, 29
...Transistor, 30...Voltage source,
31... Voltage generation circuit.

Claims (1)

[Claims] 1 a first switch circuit that switches stereo operation to monaural operation and has a first threshold voltage; and a second switch circuit that stops oscillation operation of the voltage controlled oscillator and has a second threshold voltage that is higher than the first threshold voltage.
a second switch circuit having a threshold voltage of The circuit includes a first transistor having a base coupled to the input terminal, a resistor having one end coupled to the emitter of the first transistor, and between the other end of the resistor and the base of the first transistor. a clamp circuit having at least two diodes connected in series with each other to clamp the base voltage of the first transistor;
a second transistor having a base coupled to the input terminal; a third transistor having a base coupled to a reference voltage source and differentially connected to the second transistor; and a third transistor having a base coupled to the input terminal. A receiver characterized in that it comprises a current source connected to the emitter junctions of the second and third transistors.