JPS5933944A - Circuit for preventing quantized noise - Google Patents
Circuit for preventing quantized noiseInfo
- Publication number
- JPS5933944A JPS5933944A JP14412782A JP14412782A JPS5933944A JP S5933944 A JPS5933944 A JP S5933944A JP 14412782 A JP14412782 A JP 14412782A JP 14412782 A JP14412782 A JP 14412782A JP S5933944 A JPS5933944 A JP S5933944A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- quantization
- output
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B14/00—Transmission systems not characterised by the medium used for transmission
- H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
- H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
- H04B14/046—Systems or methods for reducing noise or bandwidth
Abstract
Description
【発明の詳細な説明】
未発明は入力音発情°号?アナログ・ディジクル変換(
以下ADと称す)し、該ADされたPCM信号をディジ
タル処理する回路についての量子化ノイズ防止回路に関
する。[Detailed description of the invention] Is the input sound estrus sign not yet invented? Analog to digital conversion (
The present invention relates to a quantization noise prevention circuit for a circuit that digitally processes a PCM signal subjected to AD (hereinafter referred to as AD).
入力音響信号をタイムサンプリングしてpcu信号に変
換するのにAD回路が用られる。AD回路は入力音#信
号の振巾eft子化し、ディジタル信号に変換するもの
であり、変換ビットをNとすると、入力音響信号の振巾
は2Nの量子化区域で量子化され、対応するディジタル
数のPCM信号に変換される。量子化単位をA(単位;
ボルト)とすると、入力音響信号の最大振巾はA・2に
する必要がある。第1図は入力音響信号の振巾が小さい
場合のAD回路の動作例を示すタイムチャートである。An AD circuit is used to time sample the input acoustic signal and convert it into a pcu signal. The AD circuit converts the amplitude of the input audio # signal into a digital signal.If the conversion bit is N, the amplitude of the input audio signal is quantized in a 2N quantization area, and the corresponding digital signal is The signal is converted into a number of PCM signals. The quantization unit is A (unit;
volt), the maximum amplitude of the input acoustic signal needs to be A.2. FIG. 1 is a time chart showing an example of the operation of the AD circuit when the amplitude of the input acoustic signal is small.
第1図において、横線(al 、 (bl 、 (c)
it A D回路の量子化区域の閾値を示す。従って
、(a)〜(bl間及び(b)〜(01間がluI述の
η子化単位Aである。telは入力音響信号波形を示す
。T1〜T4はADI旦1路のサンプリングの時点であ
る。((1)はAD回U合の最下位ピントの変換出力を
示す。In Figure 1, horizontal lines (al, (bl, (c)
It shows the threshold value of the quantization area of the A D circuit. Therefore, the period between (a) and (bl and between (b) and (01) is the η conversion unit A described by luI. tel indicates the input acoustic signal waveform. T1 to T4 are the sampling points of ADI 1st pass. ((1) shows the conversion output of the lowest focus of the AD rotation U combination.
さて、第1図から明らかな通り、量子化区域近傍での入
力音響信号の微小変動は、AD回路の量子化ノイズとな
る。fFtlち、無信号11#における僅なノイズ変動
でも、AD回路の最下位のビット変動に対応する量子化
ノイズ変動となる訳である。このノイズ変動を除くため
には入力音響信号の交流バイアス点’!m (a)と(
b)の゛中間、又は(b)と(C)の中間の様KM量子
化閾値中間におけば良いが、量子化閾値の間隔Aは入力
音響信号の最大振巾の”Tである。一般にNは8〜12
であり、従ってAは微小量であり、温度変化、経時変化
等により量子化閾値の中間に安定し、て置くのは難しい
。Now, as is clear from FIG. 1, minute fluctuations in the input acoustic signal near the quantization area become quantization noise in the AD circuit. Even a slight noise variation in fFtl, no signal 11#, becomes a quantization noise variation corresponding to the lowest bit variation of the AD circuit. In order to eliminate this noise fluctuation, the AC bias point of the input acoustic signal must be '! m (a) and (
The KM quantization threshold may be set in the middle of b) or between (b) and (C), but the interval A of the quantization threshold is the maximum amplitude T of the input acoustic signal.Generally N is 8-12
Therefore, A is a minute amount, and it is difficult to keep it stable in the middle of the quantization threshold due to temperature changes, changes over time, etc.
パルス状ノイズは持続時間は短いが、振巾が比較的太き
く、たまたまサンプリングされると、これもノイズ変動
の1つとなる。人力音響信号が変化しているとき、微小
ノイズはマスキング効果により聴感上耳障りでないが、
無信号時における微小ノイズは極めて耳障9である。Pulse noise has a short duration, but a relatively wide amplitude, and if sampled by chance, it also becomes one of the noise fluctuations. When the human acoustic signal is changing, the minute noise is not audible due to the masking effect, but
Micronoise when there is no signal is extremely annoying to the ears9.
未発明は無イ3号時におけるかかる量子化ノイズの発生
を防止する回路手段ケ掃供−rるものであり、以下図面
と共に詳細トて説明1−る。What has not yet been invented is a circuit means for preventing the occurrence of such quantization noise in the case of non-operation, and will be explained in detail below with reference to the drawings.
第2図において、(1)は音響信号入力婦子、(2)は
第1クロツク入力端子、(3)はAD[!−!l路、(
4)は伝達側(財)回路、(5)及び(6)は第1及び
第2鼠子化回路、(7)は第1計数回路、(8)はシフ
トレジスタ、(9)シよANDゲートである。In FIG. 2, (1) is the audio signal input terminal, (2) is the first clock input terminal, and (3) is the AD[! -! l road, (
4) is the transmission side (goods) circuit, (5) and (6) are the first and second mouse conversion circuits, (7) is the first counting circuit, (8) is the shift register, (9) is the AND It is a gate.
AD回T#J(31は入力端子INに専ねた入力音管信
号′fr、CK端子に与えられる第1クロツク毎にタイ
ムサンプリングし、NビットのPCM信号に変換する。AD circuit T#J (31 time-samples the input sound tube signal 'fr exclusively for the input terminal IN, every first clock applied to the CK terminal, and converts it into an N-bit PCM signal.
このNビットのpcu信号は第1量子化回路(5)及び
第2量子化回路(6)のそれぞれの入力端子(DI〜D
N)K等かれ、PCM信号の値の範Ml(が量子化され
る。融ダテープの無信号録音gIi分子A:再生してい
る場合のように、入力音響信号の振巾が小さい場合(無
信号時)、(ADI〜ΔDN)のディジタルコードで構
成されるPCM信号の値が変化する範囲は小さく、第1
量子化回路(5)の出力が論理゛1”となる。人力音響
信号の振l〕がpJ1定量以上あり、PC¥信号の値が
所力!値以十、又は以下となると、第2量子化回路(6
)の出力が論理″1“′となる0
、 第1計数回路(7)は第1量子化回路(5)の出力
が論・)理・1・・のときのみ第1.り・・りを計数す
る。尚、第1クロノ々が所定数計むされると、第1引数
回路(7)の出力Q、が論理″1”となり、計数機能を
停止するよう構成する。シフトレジスタ(8)は第2量
子化回路(6)の出力を第1クロツクでサンプリングし
、シフトする。従って第2量子化回路(6)の出力が第
1クロツクの6周期の間論理1′1”であると、シフト
レジスタ(8)の出力Ql+ Q2+ Q、q u全て
論理”1”となり、その結果、アンドゲート(9)の出
力は論理″1″となり、第1計数回路(7)の出力を初
期値化する。This N-bit pcu signal is transmitted to each input terminal (DI to D) of the first quantization circuit (5) and the second quantization circuit (6)
N) K, etc., the value range Ml of the PCM signal is quantized. The range in which the value of the PCM signal, which is composed of digital codes (signal) and (ADI to ΔDN), changes is small;
The output of the quantization circuit (5) becomes logic ``1''. If the amplitude of the human acoustic signal is greater than or equal to pJ1 quantification, and the value of the PC\ signal is greater than or equal to the predetermined value!, then the second quantum conversion circuit (6
) becomes logic ``1''. The first counting circuit (7) outputs the first quantization circuit (7) only when the output of the first quantization circuit (5) becomes logic ``1''. Count the ri...ri. When a predetermined number of first chronographs are counted, the output Q of the first argument circuit (7) becomes logic "1" and the counting function is stopped. A shift register (8) samples and shifts the output of the second quantization circuit (6) using the first clock. Therefore, when the output of the second quantization circuit (6) is logic 1'1" during the 6 cycles of the first clock, the outputs of the shift register (8) Ql+Q2+Q, qu all become logic "1", and As a result, the output of the AND gate (9) becomes logic "1", and the output of the first counting circuit (7) is initialized.
伝達制御回路(4)は第1計数回路(7)の出力Qが論
理“0”のとき、入力胞子(D1〜DN)に力えられた
PCM信号を出力端子(PI〜PN)K伝達し、論f”
i’″のとき、一定のディジタル値を出力するよう構成
されている。尚、伝達用(財)回路(4)はラッチ回路
で構成されても良く、OT大入力論理″O°゛のとき第
1クロツクの周期毎にラッチ動作を行い、またOT大入
力論理tT I I+のときランチ動作を行なわず、出
力が変化しないよう構成できる。The transmission control circuit (4) transmits the PCM signal applied to the input spores (D1 to DN) to the output terminals (PI to PN) K when the output Q of the first counting circuit (7) is logic "0". , argument f”
When i''', it is configured to output a constant digital value.The transmission circuit (4) may also be configured as a latch circuit, and when the OT large input logic is O° The latch operation is performed every cycle of the first clock, and the launch operation is not performed when the OT large input logic is tT I I+, so that the output does not change.
以上の様に構成すると、無信号時、Rljち入力音響信
号の振1〕が小さい時は、PCM信号は第1量子化回路
+51 Kより量子化され、第1計数回路(7)の出力
Qが論理″1”となυ、伝達側両回路(4)はPCM信
号の伝達を停止させるから、量子化ノイズを発生しない
構成とする事ができる。勿論、無信号時にパルス状ノイ
ズが発生し、これを第2量子の6周期分以上なけれrx
第1計数回路(7)は初期値化されず、従って祖達制呻
回路(4)はP CM信号の伝達を停止した捷まである
。With the above configuration, when there is no signal and when Rlj, the amplitude 1 of the input acoustic signal, is small, the PCM signal is quantized by the first quantization circuit +51 K, and the output Q of the first counting circuit (7) is When υ is logic "1", both transmission side circuits (4) stop transmitting the PCM signal, so it is possible to have a configuration that does not generate quantization noise. Of course, pulse-like noise occurs when there is no signal, and this must be equal to or more than 6 cycles of the second quantum rx
The first counting circuit (7) is not initialized, and therefore the output control circuit (4) is at the point where it stops transmitting the PCM signal.
尚、第2@子化回路(6)の出力の代りに第1量子化回
路(5)の出力を論理反転したものを用いても既述の説
明とrri様VC7!能する。また、第1計数回路の初
期値化は、第2量子化回路(6)の出力か、又は第1量
子化回路(5)の出力の反転が第1クロツクのハr定タ
イミングのとき論理″1”Kなったとき行わさせても良
い。この場合、無化号時のパルス状ノイズは量子化ノイ
ズとなるが、定常的な量子化ノイズは防ぐ事ができる。Incidentally, even if the output of the first quantization circuit (5) is logically inverted instead of the output of the second @ childization circuit (6), the above explanation and Mr. rri's VC7! function. Further, the initial value of the first counting circuit is determined by the output of the second quantizing circuit (6) or the inversion of the output of the first quantizing circuit (5) at the constant timing of the first clock. You may have it performed when it reaches 1"K. In this case, pulse-like noise at the time of no signal becomes quantization noise, but steady quantization noise can be prevented.
このように本発明の量子化ノイズ防止回路によれば、簡
単彦回路構成で無信号時の量子化ノイズを防止すること
ができる。As described above, according to the quantization noise prevention circuit of the present invention, quantization noise can be prevented when there is no signal with a simple circuit configuration.
第1図は入力音響信号の振巾が小さい場合のアナログ・
ディジタル変換回路の動作例を示すタイムチャート図、
第2図は本発明の量子化ノイズ防止回路のブロック回路
図である。
(1)・・音響信号入力端子、(2)・・第1クロツク
入力端子、(3)・・アナログ・ディジタル変換回路、
(4)・・伝達制御回路、(5)・・第1量子化回路、
(6)・・・第2量子化回路、(7)・・・第1計数回
路、(8)・・・シフトレジスタ、(9)・・第2計数
回路。Figure 1 shows the analog signal when the amplitude of the input acoustic signal is small.
A time chart diagram showing an example of the operation of a digital conversion circuit,
FIG. 2 is a block circuit diagram of the quantization noise prevention circuit of the present invention. (1)...Acoustic signal input terminal, (2)...First clock input terminal, (3)...Analog-digital conversion circuit,
(4)...transmission control circuit, (5)...first quantization circuit,
(6)...Second quantization circuit, (7)...First counting circuit, (8)...Shift register, (9)...Second counting circuit.
Claims (1)
イムサンプリングし、PCM信号に変換するアナログ・
ディジタル変換回路と、 (b) 入力音響信号が変換された前記PCM信号の
値の範囲を量子化する第1及び第2の素子化回路と、 (cl 該卯1世子化回路の出力に基づき、第1クロ
ツク(又はこれに対応したクロック)を計数する第1計
数回路と、 (a) 前記第2景子化回路出力分前記第1クロック
(又はこれに対応したクロック)でサンプリングしてシ
フトするシフトレジスタと、(e) 前記アナログ・
ディジタル変換回路出力のPCM信号を後続するディジ
タル処理回路に伝達側(財)する伝達制菌回路と で構成され、前記第1計数回路は@紀シフトレジスタ出
力で初期値化され、前記伝達制菌回路は前記第1計数回
路出力により前記PCM信号の伝達ケ制(財)され、入
力音響信号の振巾が小さい場合(無信号時と称す)は前
記PCM信号の値の範囲がAil紀第1′Ia子イヒに
)1路により0量子化され、前記第1計数回路が前記第
1クロツクを所定だ1泪数すると、Af■紀伝達訓電1
回路は前記A D [aJ路出力のPCM信号の伝達を
中断し、入力富響(L+号の祢−rlJが797定量以
上の場合(有イt(号時と称す)は前な’P C”lν
1信号の値の範囲が前記第2量子化口路により(=f量
子化れ、塩1クロックGで基づき前記シフトレジスタに
記憶され、この妃憶因答に基づき前記第1計数回路を初
期値化し、Mfl記云達制611回路はM ’j’、
PCM信号を後続するディジタル処理回路に伝達する事
を特徴とする無信号時の量子化ノイズ防止回路C) (2)第2量子化]1工1路は、前記第1量子化回路で
量子化さtまた値の範囲以外の前記PCM信号の値の範
囲を量子化する事を特徴とする特許請求の範囲(1)に
記載の無信号時の量子化ノイズ防止回路。 (3)第1計数回路は前記第2貴子化回路出力により初
期値化される事を特徴とする特許請求の範囲(1)又は
(2)に記載の無信号時の量子化ノイズ防止回路。 (4)伝達側斜回路は前記P CM 9号を後続するデ
ィジタル処理回路に伝達するか或は所定ディジタル値を
伝達するかが前記第1計数回路出力によp制仰される事
を特徴とする特許請求の範囲(1)、(2)又は(3)
K記載の無信号時の月゛子化ノイズ防rJ=回路0[Claims] +1+(a) An analog signal that time-samples the input acoustic signal using the first clock and converts it into a PCM signal.
a digital conversion circuit; (b) first and second elementization circuits that quantize a range of values of the PCM signal into which the input acoustic signal is converted; (cl) based on the output of the rabbit conversion circuit; a first counting circuit that counts a first clock (or a clock corresponding to this); (a) a shift that samples and shifts the output of the second generator circuit using the first clock (or a clock corresponding to this); (e) the analog register;
and a transmission sterilization circuit that transmits the PCM signal output from the digital conversion circuit to the subsequent digital processing circuit, and the first counting circuit is initialized by the @ period shift register output, and the transmission sterilization circuit The circuit controls the transmission of the PCM signal by the output of the first counting circuit, and when the amplitude of the input acoustic signal is small (referred to as no-signal time), the value range of the PCM signal is within the first Ail period. When the first counting circuit counts the first clock to a predetermined value, Af
The circuit interrupts the transmission of the PCM signal of the output of the A ”lν
The value range of one signal is quantized by the second quantization path (=f) and stored in the shift register based on one clock G, and the first counting circuit is initialized based on the second quantization circuit. , the Mfl notation system 611 circuit is M 'j',
A circuit for preventing quantization noise when there is no signal, which is characterized by transmitting a PCM signal to a subsequent digital processing circuit (C) (2) Second quantization] Step 1 is to perform quantization in the first quantization circuit. 2. The quantization noise prevention circuit when there is no signal according to claim 1, wherein the PCM signal value range other than the value range is quantized. (3) The quantization noise prevention circuit at the time of no signal as set forth in claim (1) or (2), wherein the first counting circuit is initialized by the output of the second quantization circuit. (4) The transmission side diagonal circuit is characterized in that whether to transmit the PCM No. 9 to the subsequent digital processing circuit or to transmit a predetermined digital value is controlled by the output of the first counting circuit. Claims (1), (2) or (3)
Monthly noise prevention when there is no signal described in K rJ = circuit 0
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14412782A JPS5933944A (en) | 1982-08-19 | 1982-08-19 | Circuit for preventing quantized noise |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14412782A JPS5933944A (en) | 1982-08-19 | 1982-08-19 | Circuit for preventing quantized noise |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5933944A true JPS5933944A (en) | 1984-02-24 |
JPH0412653B2 JPH0412653B2 (en) | 1992-03-05 |
Family
ID=15354824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14412782A Granted JPS5933944A (en) | 1982-08-19 | 1982-08-19 | Circuit for preventing quantized noise |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5933944A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5724354B2 (en) | 2010-12-16 | 2015-05-27 | 大日本印刷株式会社 | Soft drink filling method and apparatus |
JP6439921B2 (en) | 2013-11-14 | 2018-12-19 | 大日本印刷株式会社 | Bottle sterilization method and apparatus |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58165441A (en) * | 1982-03-26 | 1983-09-30 | Hitachi Ltd | Pcm signal encoder |
-
1982
- 1982-08-19 JP JP14412782A patent/JPS5933944A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58165441A (en) * | 1982-03-26 | 1983-09-30 | Hitachi Ltd | Pcm signal encoder |
Also Published As
Publication number | Publication date |
---|---|
JPH0412653B2 (en) | 1992-03-05 |
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