SU1109848A1 - Device for coding audio signals with inertial companding - Google Patents

Abstract

1. DEVICE, INTEGRATED INSIDE COMPANDING SOUND SIGNAL CODING, containing scale amplifier d serially connected signal source and sampling and storage unit, to the synchronization input of which the first synchronizer output is connected, the second output of which is connected to the synchronization input of the analog-digital converter (A / D converter). the output of which is connected to the first input of the code generator, to the synchronization input of which the third output of the synchronizer is connected, which is distinguished by the fact that There are speeds, sequentially connected comparators and a scale code definition block, the first output of which is connected to the second input of the code generator, and the second output of the KQfta definition block of the scale are connected to the control input of the scale amplifier, to the information input of which subcampmen the output of the discretization block and stored, ti,: / nor, and the output of the large-scale amplifier is connected to the input of the comparator unit and the signal input A1SCH, the output of which is a higher bit connected to the sign input of the op unit edeleni scale code to the input counting pulses, and synchronizing input memory entry zeroing memory entry and setting the scale for determining the trigger code block are respectively connected fourth, fifth, sixth, and seventh outputs of the synchronizer. 2. The device according to claim 1, characterized in that the scale code detection block includes a recording block i block, a counting pulse barring block and a series of SL connected pen element, a scaling indicator sign forming unit, the second OR element, a bar inhibit forming unit, block no memory zeroing, memory block, counting pulse shaping unit, reverse pulse shaping unit, block about: 0 reverse control, reversible counting unit, counting block 00 4 :; and a block for removing counting pulses, the second input of which is connected to the output of the first element OR, 00, and the output of block for blocking counting pulses is connected to the second input of the second element OR, to the second input of a block of forming pulses per version, to the second input of the forming block of counting pulses, to the third input of which the second output of the counting restriction block is connected, and the second output of the block of forming the counting pulses is connected to the first input of the block of the restriction of counting pulses, the output of which is connected

Description

to the second input of the reverse control unit, while the output of the first element OR is connected to the second input of the memory unit, the output of which is connected to the second input of the formation unit of the scale change sign and the first input of the recording inhibit block, the output of which is connected to the third input of the memory unit the second and third outputs of the reversible counting unit are respectively the second: the first outputs of the scale code definition block, and the input of the first OR element, the second input of the counting pulses prohibiting unit, the second input of the memory zero inhibitor block These second, third and fourth inputs of the inhibit pulse shaping unit, the second input of the write inhibitor block are respectively the information input, the input of counting pulses, the sign input, the trigger setup input, the memory zeroing input and the scale code detection memory input.

The invention relates to a technique for transmitting information and is intended for use in systems for the discrete processing of high-quality audio signals.

A device for encoding compressed audio signals is known, containing a series-connected amplifier, switch, analog-to-digital converter (ADC), an output register, as well as a decisive block and the Cl 3 synchronizer. However, the known device has low speed due to the fact that the signal is encoded in two cycle.

Closest to the proposed technical solution is a device for encoding audio signals, containing a large-scale amplifier and a serially connected signal source and a sampling and storage unit, to the synchronization input of which the first synchronizer output is connected, the second output of which is connected to the synchronization input of the ADC, the output of which is connected to the first input of the code former, to the synchronization input of which the third output of the synchronizer is connected, as well as the prohibitory shift block, the transducer block position code, serially connected code register, decisive unit, low-order inhibitor and universal register, and serially connected amplifier, shear pulse shaping unit and gate, to the second of which INPUT the first output of the shear inhibit unit is connected, the second output of which is connected to the second the entry of the block of the low-order bit and through the block of conversion of the positional code to the second input of the shaper of the code, to the third input of which the first output of the amplifier is connected, to the input

0 which is connected to the output of the sampling and storage unit, and the second output of the amplifier is connected to the first input of the large-scale amplifier and the first input of the switch unit,

S whose output is connected to the input of the ADC, while the output of the valve is connected to the second input of the universal register, the output of which is connected to the second input of the large-scale

0 amplifier, the output of which is connected to the second input of the switch unit, to the synchronization input of which is connected the fourth output of the synchronizer, the fifth, sixth, seventh and

5, the eighth outputs of which are connected respectively to the synchronization inputs of the universal register, the prohibitory shift block, the decisive block of the code register, to the input of which the output of the ADC CZ is connected.

A disadvantage of the known device is the low speed associated with the need to process each sample signal in two cycles and a significant delay in signal propagation in the device. The purpose of the invention is to express speed. The day of achieving the set goal in the device for encoding audio signals with inertial companding, contains a large-scale amplifier and serially connected signal source and a sampling and storage unit, to the synchronization input of which the first synchronizer output is connected, the second output of which is connected to the synchronizing input of the ADC, the output of which is connected to the first input of the shaper code, to the sync input of which the third output of the synchronizer is connected, is entered in series e comparators unit and a scale code detection unit, the first output of which is connected to the second input of the code generator, and the second output of the scale code detection unit is connected to the control input of the scale amplifier, to the information input of which the output of the sampling unit and storage is connected and the output of the scale amplifier is connected to the input of the comparators block and the signal input of the ADC, the output of which is higher than the th digit of which is connected to the sign input of the block for determining the scale code, to the input of the counting pulses, and also to the synchronization input of the PC The four, five, sixth and seventh outputs of the synchronizer are connected, respectively, to the memory zeroing input and to the installation input of the trigger of the scale code detection unit. The scale code detection block contains a block of recording prohibition, a block of blocking counting pulses and a serially connected first element OR, block forming a sign of changing the scale, second block OR, block forming a ban pulse, block zeroing memory, block memory, block counting them pulses, a reverse pulse shaping unit, a reverse control unit, a reverse counting unit, a counting limit unit and a blocking unit for removing counting pulses, the second input of which is connected to the output of the first OR element, and the output of the block Removing the prohibition of counting pulses connected to the second input of the second element And to the second input of the form block, the world of the pulses to the second input of the lock forms the counting pulses, the third input of which is connected to the output of the limiting block of the count, and the second output of the block forming the counting pulses to the first the input of the counter count inhibitor block, the output of which is connected to the second input of the control unit of the reper, while the output of the first element OR is connected to the second input of the memory block, the output of which is connected to the second input the scale change feature generating unit and the first input of the write inhibiting unit, the output of which is connected to the third input of the memory unit, the second and third outputs of the reversible counting unit are the second and first outputs of the scale code definition unit, and the input of the first element OR, the second input counting pulses prohibition unit, the second input of the memory zeroing prohibition unit, the second, third and fourth inputs of the prohibition impulse generation unit, the second input of the recording prohibition unit are respectively an information input, Odom counting pulses, sign input input for setting a trigger input and memory zeroing input sync block memory for determining the scale code. Figure 1 shows a block diagram of a device for encoding audio signals with inertial companding; Fig. 2 shows the structure of a circuit for determining the scale code. A device for encoding audio signals with inertial companding contains a signal source 1, a sampling and storage unit 2, a scale amplifier 3, an ADC 4, a driver, a comparators block 6, a scale code determining unit 7, a synchronizer 8. The scale code determining unit 7 contains the first element OR 9, block 10 of formation of the sign of a scale change, the second element OR 11, block 12 of the formation of a prohibition pulse, block 13 of the prohibition of memory zeroing, block 14 of a memory, block 15 of forming a counting pulse, block 16 of forming a reverse pulse, block 17 systematic way ratchet, a reversing unit 18 accounts, bills limiting unit 19, the unit 20 removably prohibition countable pulses. block 22 for block 21 of the prohibition of recording and reta counting pulses. The device works as follows. The change in the gain factor of the scale amplifier 3 occurs only in two cases: if the signal sample values pass through the ADC 4 quantization range, the transfer factor of the scale amplifier decreases twice, if during the time interval between two successive transitions of the signal through the middle level, there was no confirmation the transmission coefficient of the scale amplifier 3 set in the previous time interval, at least once, then the transmission coefficient of the scale amplifier 3 is doubled. This algorithm is implemented in block 7 for determining the scale code. An analogue audio signal from the output of source 1 of the signal is fed to the input of sampling and storage unit 2, in which, when a clock pulse is received from synchronizer 8, it is sampled and the readout value is stored for the full conversion time to digital equivalent. The storage time is 20.8 mks. Next, a constant signal reference voltage is fed through a large-scale amplifier 3 to the signal input of the A / D converter 4 and to the input of block 6 of the comparators. At the initial moment of time, the transfer coefficient of the scale amplifier 3 can have any allowed value (1,2,4,8). When the clock pulse from the second clock input of the synchronizer 8 appears on the ADC 4 nespBoro clock input, the ADC 4 determines the value of the most significant bit of the code that is recorded when the second clock pulse arrives in the register in succession for balancing this block. The value of the first codeword size characterizes the polarity of the signal reading and the moment of its change is the signal transitions through the mean value. Information from the output of the high bit of the ADC 4 is fed to the sign input of the block 7 for determining the code of the scale. After the delay time of the comparators, the output of block 6 of the comparators contains information corresponding to the hit of the signal sample value either by the thresholds of the triggering of the 8 comparators, or over the quantizing range. In this case, three situations are possible: the count value is less than the threshold voltage at all the comparators for one signal polarity, the count value is between the thresholds, the signal count is clipped. In the first case, the code combination 00 is set at the output of the 6komparator block, in the second and in the third - 11. The combination 00 indicates that the sample size is less than a quarter of the ADC 4 quantization range and should be increased. Combination 10 is permitted and indicates that the signal sample occupies most of the quantization range, i.e. ADC 4 is used in the best way. Combination 11 corresponds to signal clipping, which must be immediately prevented, prioritizing decreasing the transfer coefficient of a large-scale amplifier 3. Information from the comparators block 6 is fed to the information input of the scale code definition block 7, where it is processed according to the indicated algorithm, resulting in the second the output of block 7 is set to such a signal, which, arriving at the control input of the scale amplifier 3, sets the required transmission coefficient. After the time interval required for the termination of the transients in the large-scale amplifier 3, the clock input of the A / D converter 4 from the second output of the synchronizer 8 receives another ten clock pulses necessary to complete the one-bit counterbalancing cycle. The digital code from the output of the A / D converter 4 is fed to the first input of the imaging unit 5 of the code, the second input of which has the reference scale code set from the first output of the scale code detection unit 7. According to the pulse coming from the third output of the synchronizer 8 to the synchronizing input of the kohr 5 generator, the information from the last input is rewritten into the memory register of the former of the 5th code and fed to the output of the device. The scale code determination unit 7 operates as follows. Information from the block of 6 comparators through the first element OR 9,

combining information for positive and negative samples of the signal, is fed simultaneously to the second input of memory block 14, to the second input of block 20 from disabling the counter pulses, and to the first input of block 10 to form a sign of changing the scale. In the case of clipping a signal in the ADC 4 quantizer, code combination 11 appears at the output of the first element OR 9, which causes the output of the ZI-NO coincidence element in block 20 of the removal of the prohibition of counting pulses to appear logic level zero. This signal acts on the counting pulse shaping unit 15 and on the reverse pulse shaping unit so that at the second output of the pulse shaping unit a level of logical unit appears that opens the counting pulse prohibitor unit 22. At the output of the reverse pulse shaping unit 16, a logic unit level is set which switches the reverse control unit 17 in such a way that the counting pulse arriving at the input of the reversing counter input of the reverse counting unit 18 reduces the counter state by one. The code from the second output of the reverse counting unit 18 is fed to the control input of the large-scale amplifier 3, the coefficient of which is doubled. After the termination of the transient process in the large-scale amplifier, the ADC 4 finishes balancing the altered signal voltage, and the digital equivalent goes to the first input of the driver 5 of the code. When a clock code from the third output of the synchronizer 8 arrives at the clock input of the generator, the code of the count value from the first input of the generator 5 of the code and the code of the scale from its second input is written into the memory register and then goes to the output of the entire device. of the first element OR 9 has not changed, then the operation of the block 7 for determining the code of the scale is similar until the dispute until the output of the first element OR 9 fails to allow the combination 10

The statistical properties of the signal are such that the latter case can

It is only when the device is turned on. In the tracking mode, one switching of the reference scale is sufficient, since the steepness of the change in the amplitude of the sound signal has a finite value.

Let the magnitude of the voltage of the reference signal at the output of the scale amplifier 3 become such that it falls between the thresholds of the output signal rccount. In this case, at the output of the first element OR 9, the code combination TO appears at least once during the transition time of the signal through the average value. At the same time, information from the output of the first element OR 9 is fed to the second input of the memory block 14, where it is recorded with the arrival of a memory sync pulse arriving at the third input of the memory block 14 through the open recording inhibit block 21. As soon as the code combination 10 is in accordance with the output of memory block 14,

5, the write inhibit block 21 is locked, thus preventing the code from being rewritten in the memory block 14. In this case, the coincidence circuit is triggered in the characteristic formation block 10.

At the output of the second scale and at its output a logic zero level appears, which is fed to the first input of the second element OR 11. At the output of the second element OR 11, a negative pulse occurs, affecting the trigger in the block of the formation of a prohibition impulse 7-4, which, operation, captures the fact of the occurrence of the allowed combination 10 and forbids zeroing of memory block 14 with the arrival of a change signal pulse, aka, since the first input of block zero inhibitor appears logical level zero. At the same time, at the output of block 20 for removing the prohibition of the counting pulse, the level of the logical unit is set, which is fed to the second input of the block 15 to form the counting pulse 50, at the second output of which a level of logic zero occurs. This level, entering the first input of block 22 of the counting pulses, closes the last, after which the counting pulse from the fourth output of the synchronizer 8 to the reverse control block 17 remains in the same state 9 regardless of the state of the reverse control block 17, i.e. . regardless of the control command, which comes from the output of the reverse impulse generation unit 16. Thus, at the output of the reverse counting unit 18, the information does not change, and the transmission coefficient of the scale amplifier 3 remains constant. The voltage of the signal samples from the output of the amplification amplifier 3 is fed to the signal input of the A / D converter 4, which performs their analog-to-digital conversion, and the output codes from the first output of the A / D converter 4 are fed to the first input of the code 5 generator, which are recorded by its clock pulses the synchronization input from the third output of the synchronizer. 8 If the input signal level decreases, the voltage value of the signal samples may become such that the comparators trigger thresholds for any polarity of the reference value are not reached. At the same time, the output of the first element OR 9 never for the time between successive transitions of the signal through the average value does not allow the allowed code combination 10. The block 10 of forming the sign of the scale change in this case will never work, and the block of the formation of the inhibit impulse never will change its state. Therefore, with the arrival of a pulse of a change in the sign of the countdown from the output of the higher bit of the A / D converter 4, the memory block 14 is zeroed through the open memory zero inhibitor block 13. After that, the block 10 forms a sign of a scale change, i.e. At its output, a logic zero level appears, which through the second element OR 1.1 is recorded in the prohibition impulse generation unit 12, thus locking the interlocking unit 13. At the same time, the counting pulse forming unit 15 is activated, affecting the reverse pulse shaping unit 16 and the counting pulse inhibiting block 22. The reverse impulse generation unit 16 imposes a logical zero level on the reverse control unit 17, under the influence of which the counting pulse from the output of the open unit 22 prohibiting the counter impulses goes to the summing input of the reversing counter in block 18 of the reverse counting, the output code of which will increase by one, which will result to a corresponding increase in the transmission coefficient of the scale amplifier 3 twice. The coefficient of the voltage gain of the reference signal does not change until the next pulse of the counting sign changes. However, with the arrival of the count with a new sign, a negative pulse from the sixth output of the synchronizer 8 arrives at the third memory reset input, RS- the trigger is zeroed, which ensures preparation of the scale code definition block 7 for analyzing the next time period between successive transitions of the signal through the middle level. The memory zeroing pulse arrives at the input of the block The inhibit impulse generation signal 12 at each sample of the signal. But the trigger is zeroed only for reference with a new sign. This is achieved by the fact that the required impulse is extracted by the 2I-NO coincidence element, to the other input of which a positive impulse is generated, generated by the second RS-trigger, which is set to one by a change of sign pulse, coming from the sign output of the A / D converter 4, and sent to zero by the trigger of the trigger, arriving at the third output of the inhibitor impulse generation unit 12 from the synchronizer 8. Operation of the device the written mode continues until the time of the analysis, i.e. during the time between successive changes in the sign of the samples, at the output of the first element, code combination 10 or the reversal counting unit 18 does not completely fill out. The boundary values of the numbers in the reversible counter are specified by the count limit block 19. When a combination counter 00 and 11 appears at the output of the reversible counter, the counting restriction block 19 causes logic zero levels to block 20 for removing counting pulses and to block 15 for generating counting pulses, thus prohibiting further changes to the control code at the output of block 7 for determining the scale code, those. the emergence of parasitic amplitude modulation of the signal. If at the next time interval between successive changes in the sign of the signal at the output of the first element OR 9 at least one combination 10 appears, then the block 10 forming the sign of the scale change through the second element OR 11 and the block 12 forming the prohibition impulse causes block 13 no memory zeroing, the logical zero level, thereby prohibiting the memory unit 14 to be zeroed with the arrival of a change in sign pulse on the prohibition impulse generation unit 12 and the memory zero inhibit unit 13. At that, the counting pulse generation unit 15 prohibits the passage of the counting pulse through the counting pulse block 22, and the state of the reverse counting unit 18 does not change (as required by the conversion algorithm). The state of block 18 of the reversing account will remain unchanged until either a signal clipping, i.e. at the output of block 6 of the comparators, combination 11 does not appear, or the signal level decreases so that at the output of block 6 of comparators

n 48 a new combination of 00 for the entire period of analysis of the signal samples in block 7 for determining the scale code. In both cases, the operation of the scale code detection unit 7 will be carried out as described, until the permitted combination 10 has been generated, which is written in the memory block 14. The presence of code pattern 10 in memory block 14 indicates the presence of a tracking mode for the subdomain of the change in the envelope of the audio signal. Thus, inertial companding of samples is performed. The proposed device for encoding audio signals with inertial companding has a shorter time for a complete conversion of the reference signal. This is due to the fact that the processing of information from the output of block 6 of the comparators according to the inertial conversion algorithm, without resorting to the analog-to-digital conversion of the signal in the first encoding cycle, always takes less time and, consequently, increases the speed of the device. To blocks 3 Lpb about ab To block 5 Otklo al From SJIOM.

Claims (2)

1. A DEVICE FOR CODING AUDIO SIGNALS WITH INERTIAL COMPANDING, containing a large-scale amplifier ¢ 1 signal source and a sampling and storage unit, to the synchronizing input of which the first output of the synchronizer is connected, the second output of which is connected to the synchronizing input of an analog-to-digital converter (ADC) , the output of which is connected to the first input of the code generator, to the synchronizing input of which the third output of the synchronizer is connected, characterized in that, in order to increase In order to improve performance, a series-connected comparator unit and a scale code determination unit are introduced into it, the first output of which is connected to the second input of the code generator, and the second output of the scale code determination unit is connected to the control input of the scale amplifier, to the information input of which V is the output of the sampling and storage unit, and the output of the large-scale amplifier is connected to the input of the comparator unit and the signal input of the ADC, the high-order output of which is connected to the sign input of the scale code determination unit, to the input of the counting pulses, and also to the memory clock input, input zeroing the memory and the trigger setup input of the scale code definition block are connected to the fourth, fifth, sixth and seventh outputs of the synchronizer, respectively. 2. The device according to claim 1, characterized in that the scale code determination unit comprises a recording prohibition unit, counting pulse prohibition unit and a serially connected first OR element, a scale change indication generating unit, a second OR element, a prohibition pulse shaping unit, a zero prohibition unit a memory unit, a memory unit, a unit for generating counting pulses, a unit for generating a reverse pulse, a reverse control unit, a reverse counting unit, a counting restriction unit, and a block for counting Pulses being disabled, to the second input of which is connected the output of the first OR element, and the output of the counting pulse inhibit blocking unit is connected to the second input of the second OR element, to the second input of the pulse generation unit per ver, to the second input of the counting pulse generation block, to the third input of which the second output of the counting restriction block is connected, and the second the output of the counting pulse generation unit is connected to the first input of the counting pulse inhibit block, the output of which is connected SU ,,., 1109848 to the second input of the reverse control unit, while the output of the first OR element is connected to the second input of the memory unit, the output of which is connected to the second input of the scale change sign formation unit and the first input of the write inhibit unit, the output of which is connected to the third input a memory block, the second and third outputs of the reverse counting unit, respectively, the second and first eniya memory, second, third and fourth inputs of unit pulse shaping ban, the second input of the recording prohibition information are respectively input, input counting pulses, sign input input latch setup, reset input and memory input synchronization code determination unit scale.