GB1266047A - - Google Patents

Abstract

1,266,047. Facsimile transmission systems. TELEFUNKEN PATENTVERWERTUNGS G.m.b.H. 5 June, 1969 [12 June, 1968], No. 28614/69. Headings H4F and H4P. Continuously variable facsimile signals are sampled at regular intervals and quantized to provide a series of n-bit words. To reduce redundancy in the series some of the words representing black and white levels are converted to single bit form, the remaining words being unchanged. In a first embodiment, Fig. 2, the analogue signals NF pass to an analogue-digital converter 1 and to a circuit comprising threshold circuit 7, 6 and delay 10 giving an output d when NF is grey (apart from the grey inherent in a black to white transition). Converter 1 generates 4-bit words at a rate b, the most significant bit passing direct to m-bit shift register 12. The other 3 bits pass to the next 3 cells of the register only when gate 13 is enabled, as it is when bi-stable FF is set by d. Thus during grey signals, and subsequently until FF is reset, 4-bit words are read in to register 12, otherwise only single bit words are read in, the register being stepped at a rate 4b or b as appropriate. When register 12 is full its contents are transferred to store 2. The sampling pulses t (rate b) are counted at 19 from the instant when NF is no longer grey, i.e. when d is absent, but FF is not yet reset. If the counter, which is reset should NF again become grey, reaches a set count, e.g. 24, FF is reset by unit 14 when register 12 is full, so inhibiting gate 13. Unit 14 develops a signal indicating whether the next following register word stored in 2 from register 12 contains 4-bit words or 1-bit words, and how many register words with similar coding precede it. The signal also indicates how many places of the present register word contain 1-bit words. To avoid the need for this latter information the circuit of Fig. 2 may be modified, Fig. 3 (not shown), so that FF can change state only when the register 12 is full. This entails the use of m-bit delays between the a-d converter 1 and the register. To reconstitute the analogue signal an inverse process is employed, Fig. 6 (not shown). In a further embodiment, Fig. 4 (not shown), an analogue signal (NF) is quantized, successive resulting n-bit words being compared (26). If adjacent words are identical a counter (31b) is incremented by 1, but if they are different the second of the words, together with the count, is passed to a store (via 34). The store's output is reconverted to analogue form by a circuit, Fig. 5 (not shown), in which the n-bit word is passed to a digital-analogue converter fed by clock pulses which also decrement the count. When the count reaches zero the next n-bit word and count are read from the store.