JPS5933546A - Digital comparator - Google Patents

Abstract

PURPOSE:To set a comparison data into an optional bit number with a sole comparator, by connecting an FF to an output of the comparator, and feeding back the output to the input side of the comparator. CONSTITUTION:Comparison data A, B inputted to a comparator 10 are used as series data and the comparison outputs A>B, A<B of the comparator 10 are inputted to FFs 11, 12. Further, an output Q of the FF11 is fed back to an input terminal a0 of an LSB section of the comparator 10 and the output Q of the FF12 is fed similarly back to an input terinal b0 of the LSB section of the comparator 10. Then, each one bit is compared by the LSB of the data A, B by inputting the clock pulse CP synchronized with the input data A, B in series to a clock terminal T of the FFs 11, 12. Further, the output data is latched to the FFs 11, 12 in synchronizing with the clock pulse, and the output is fed back to the input side of the comparator 10. The newest result of comparison is kept through the repetition.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparator that compares the magnitude of digital data.

Conventionally, when comparing the size of digital data, the first
As shown in the figure, a comparator (10) is provided to compare n-bit digital data (n=4 in the example in Figure 1), and two parallel input data A and B to be compared are each input to a comparator (1o). The input terminals (ao,) to (
a3) t (bx) ~ (bs) Input data is input in ascending order from the LS-p-, and is compared by the comparator (10), and output co- according to the magnitude relationship between A and B.
There is one that takes out C2.

In this case, the comparator (10) calculates that when the two input data A and B are A)B, each output Co-C2 is Co=1°Cx=0, C2=O, and also when A=B. When output Co=0, C+==1, C2=0, A(B
When , the output C0=0, C1=O, C,=0.

However, in such conventional comparators, the pit length that can be compared is limited by the number of input bits of the comparator (10) that compares the input data.
When comparing two input data with longer bit length, it is necessary to use multiple comparators.
Further, there is a drawback that various peripheral circuits must be added to connect them.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above. Each comparison output of the comparator is latched by a flip-flop, and each output of these flip-flops is fed back to the input side of the comparator. The purpose is to provide four digital comparators that can compare input data of any pit length using only one comparator.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a circuit diagram without showing a digital comparator according to an embodiment of the present invention. In the same figure, (10)
is a comparator similar to the conventional one, and this input terminal (n
A serial input signal A is input as a comparison signal to the input terminal (bl), and a series input signal B is input to the input terminal (bl) as a comparison signal. (11) and (12) are the respective comparison outputs (A>B) of the comparator (10)
1 (A<8), and the clock terminals (T) of these flip-flops (11) and (12) have a clock synchronized with the two serial input data A and I3 to be compared. Pulse CP is input. Then, the output Q of the 7 flip-flop (H) is connected to the input terminal (piece) of the LSB part of the comparator (10), and the output Q of the flip-flop (12) is connected to the input terminal (piece) of the LSB part of the comparator (10).
) are fed back to the input terminals (bo) of the respective input terminals (bo). In addition, each 7 lip 7rI tube (11), (12
) is input to the NOR circuit (13), and the output of the flip-flop (11) (7) is the output CO whose output Q corresponds to the output (A>11) of the comparator (10).
Take out as 11. Ru. In addition, the output of the NOR circuit (13) is the output CI corresponding to the A and 8 outputs (A=n) of the comparator (10), and the output Q of the flip-flop (12) is
are respectively taken out as the output C2 corresponding to the output (1c<n) of the comparator (1o). Note that a reset pulse RP is input to the reset terminals (R) of the Raritub flops (11) and (12).

In this way, the comparison data A and 13 input to the comparator (10) are serial human data, and the comparator (10
), the comparison outputs (A>B) and (A<B) are input to flip-flops (11) and (12). Then, the output Q of this clip 70 tube (11) is fed back to the input terminal (-0) of the LSI 3 part of the comparator (10), and similarly the output Qt of the 7 lip-flop (12) - the LSB part of the comparator (10) is fed back. Input terminal (b
Provide feedback to O). Therefore, the clock pulse CP synchronized with the serial input data A, B is applied to the clock terminal (T) of each flip-flop (11), (12).
By inputting 1. from I and Sll of comparison human power data A and B for each clock pulse.・The output data is compared bit by bit and latched in flip-flops (11) and (12) in synchronization with the lock pulse, and this output is fed back to the input side of the comparator (10). At the next clock pulse CP, the next input bit is compared 2 bits at a time with the output of the comparator (10) obtained by feedback with the previous clock pulse, and depending on their magnitude, the comparator (from 1 to 1) is compared. The result is output, and the output data is transferred to the flip-flop (1
1) and (12). Thereafter, by repeating these operations, the time t of each clock pulse CP
l, t2. The transition of input/output data between the input data A, 13 synchronized with , and the outputs Co to C2 whose magnitudes are compared is shown in Table 1 below.

Table 1, that is, Table 1 shows the flip-flop (11), the NOR circuit (
13) and the output Co, C of the 7 lip flop (12)
Time tl + t2t of each clock pulse of 1 and C2
Showing the comparison results of the comparators in...
Serial input data A and B to be compared and 1-bit input data Al and Bt are input to the comparator (10).
If one primary input is applied, each input bit causes each flip-flop (11) and (12) before the clock input.
) is input to the input terminals (&0) and (bo
), the comparison results are always updated or maintained when the latest input data At, T3t is received. In this way, it is possible to compare data of any number of bits with one comparator (10), and as a result, the reset pulse U and reset pulse RP are 7 and 70 bits (it) at the reset terminal (12). It remains valid until it is entered in

In addition, in the above example, the case of serial data of one channel was shown as comparison data, but parallel BCD
In other words, it is also possible to implement the 91 channel as a 2-data comparator composed of 4 bits using exactly the same means.

As described above, according to the present invention, 7 lips and 70 tubes are connected to the output of the comparator, and the output is fed back to the input side of the comparator.
Comparison data can be set to any number of bits using only one comparator, and the number of components required to implement the circuit is also smaller than that of conventional circuits, which has the effect of simplifying the circuit.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing a conventional digital comparator.
FIG. 2 is a circuit diagram showing a digital comparator according to an embodiment of the present invention. (10)... Comparator, (it), (12)
ψ...Flip-flop, (13)--Nor circuit. Agent Makoto Kuzuno - Mr. Commissioner of the Japan Patent Office■, Small case indication Japanese Patent Application No. 57-144409 2, Title of the invention Digital comparator 3, Part 5 to representative Kata Yuni of the person making the amendment, Invention of the specification subject to the amendment Detailed omission column 6, content of amendment [(bl) to (b:1
')j is corrected as r(bo"t~(b3)J. That's all.

Claims (1)

[Claims] In a comparator that compares the magnitude of digital input data, a flip-flop 70 is provided to latch each comparison output of the comparator, and each output of these flip-flops is fed back to the input side of the comparator, so that the flip-flop I made it possible to extract each output as a comparison output/)\t1
A digital comparator with t.