JPS5931250B2 - Encoder-decoder supervisory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monitoring device for encoders and decoders in PCM terminal equipment.

In conventional PCM terminal equipment, an encoder/decoder is commonly used for a plurality of communication channels.

Therefore, as a monitoring method for the encoder and decoder, a specific communication path is used and monitoring is performed when there is no communication on that communication path.

Alternatively, by taking advantage of the high speed of the encoder and decoder, monitoring is performed using idle time when encoding and decoding are not being performed.

However, with recent advances in LSI technology, encoders and decoders have been integrated into a single chip, and it has become economically possible to use separate encoders and decoders for each channel.

In such an individual channel encoder/decoder configuration,
The monitoring system must also be inexpensive enough to match the cost of the encoder and decoder, and the conventional system for determining whether a call has been missed has a complicated circuit configuration and is economically disadvantageous.

Furthermore, since the encoder and decoder for each individual communication path handles only one communication path information, the speed may be slow, and by utilizing this feature, it is possible to implement the system into an LSI.

Therefore, if monitoring is to be carried out using idle time as in the past, it is necessary to increase the operating speed of the encoder and decoder, and this method is effective as a monitoring method for the encoder and decoder of individual communication paths. It wasn't something.

Therefore, an object of the present invention is to improve the above-mentioned drawbacks of the prior art, and its feature is that the analog signal of the encoder input or decoder output for each channel is compared with a predetermined level close to the DC zero level. A comparator circuit that outputs a logic value 1 when is smaller than the level and a logic value O when it is smaller than the level, and whether a specific code bit of the encoder output or decoder input matches the output of the comparator circuit. The encoder/decoder monitoring circuit has a coincidence detection circuit for each communication path for detecting a match, and a means for each communication path for generating an alarm when the comparison result does not match.

Therefore, according to the present invention, by using the information itself passing through the encoder and decoder, monitoring can be performed without determining whether there is a call or no call, and the operating speed of the encoder and decoder is used for monitoring. There is no need to speed up the process.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the encoder monitoring system according to the present invention, in which 1 is an encoder input terminal, 2 is an encoder, 3 is an encoder output terminal, 4 is a comparison circuit, 5 and 6 are comparison output terminals, 7 and 8 are delay elements, 9 is a channel pulse input terminal, 10 is a digit pulse input terminal, 11 is a sign bit extraction circuit, 12 is a coincidence detection circuit, 13 is an alarm prohibition circuit, and 14 is an alarm terminal.

FIG. 2 shows an embodiment of the decoder monitoring system, in which 15 is a decoder input terminal, 16 is a decoder, 17 is a decoder output terminal, and 18 is a decoder monitoring system.
is a comparison circuit, 19 and 20 are comparison output terminals, 21 is a channel pulse input terminal, 22 is a digit pulse input terminal,
23 is a code bit extraction circuit, 24 is a delay element, 25 is a coincidence detection circuit, 26 is an alarm prohibition circuit, and 27 is an alarm terminal.

Next, the operation of the present apparatus will be described. Since the principles of encoder monitoring and decoder monitoring are the same, only the encoder will be described.

The most fragile parts of an LSI chip are the input and output parts.

When these parts are broken, an output that is unrelated to the input signal generally appears at the output.

The easiest way to detect this is to detect whether the positive/negative of the input signal matches the positive/negative of the output signal.

PCM encoders currently used for communication express one sample value with an 8-bit digital code.

The first bit of these is a sign bit, which is "1" when the signal is positive and "0" when it is negative.

Therefore, a circuit 4 (first
If the input signal is positive, ``1'' is output to the terminal 5, and if it is negative, 0'' is output to the terminal 5.

However, since the positive/negative determination circuit of the encoder itself may have an offset, this comparison is not performed when the input signal is near zero.

That is, the input signal changes from -vH to v as shown in FIG.
When it is between H, outputs 1'' to terminal 6 and connects circuit 13.
Prohibits alarm transmission.

This vH may be arbitrarily determined between the determination voltage of the second segment and the overload level.

Note that since there is a delay between the input and output of the encoder, it is necessary to correct this with seven and eight delay elements.

Note that even if the encoder and decoder include a channel filter and AV, monitoring can be performed using the same principle.

As described above, the present invention is suitable for monitoring LSI encoders and decoders, and is effective in detecting abnormalities in operation with a simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an encoder monitoring device according to the present invention, FIG. 2 is a block diagram of a decoder monitoring device according to the present invention, and FIG.
The figure is an input/output relationship diagram for explaining the monitoring operation. 1... Encoder input terminal, 2... Encoder, 3... Encoder output terminal, 4... Comparison circuit, 5, 6... ... Comparison output terminal, 7, 8...
... Delay element, 9... Channel pulse input terminal, 10... Digit pulse input terminal, 11
. . . Sign bit extraction circuit, 12 . . . Coincidence detection circuit, 13 . . . Alarm prohibition circuit, 14
......-Alarm terminal, 15...Decoder input terminal, 16...Decoder, 11...Decoder output terminal, 18... Comparison circuit, 19, 20
... Comparison output terminal, 21 ... Channel pulse input terminal, 22 ... Digit pulse input terminal, 23 ... Sign bit extraction circuit, 24.
... Delay element, 25 ... Coincidence detection circuit,
26... Alarm prohibition circuit, 21...
Alarm terminal.

Claims (1)

[Claims] 1 Compare the analog signal of the encoder input or decoder output for each communication path with a predetermined level close to the DC zero level, and when the analog signal is higher than that level, the logic value is 1, and when it is smaller than the level, the logic value is O. a comparison circuit that outputs a signal, a coincidence detection circuit for each communication channel that detects whether a specific code bit of the encoder output or decoder input matches the output of the comparison circuit, and an alarm that generates an alarm when the comparison result does not match. means for each generated communication path.