SU1332546A2 - Device for checking the quality of a digital signal - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to expand the functionality by determining the address of the selected channel and the duration of its operation. The device contains input processing channels 1, consisting of (counters 2 and 4, PLNI-NE 3, RS flip-flop 5, amplitude detector 6, fjLl L1 RL S el oo co to e 4 N) | 3ek-I

Description

integrator 7 and driver 8 pulses. It contains switches 9, 10, 22 and 26, DAC 11, comparators 12 and 15, adders 13 and 27, threshold unit 14, keys 16, 17, 20 and 32, reversible counter 18, inverters 19 and 21, el-OR 23 and 29, r-24 pulses, dividing blocks 25 and 35 of frequency, you are E-28, decoder 30, counters 31 and 34, buffer register 33 and NOT 36 e-mail. When the input signal is either speech signal or noise in the passband of a standard radio-tele1

The invention relates to telecommunications, can be used to automatically select a busy radiotelephone communication channel with a maximum output signal level or a free radio telephone channel with a minimum noise level, and is an improvement of the device according to the author. St. No. 1100737.

The purpose of the invention is to expand the functionality by determining the address of the selected channel and the duration of its operation.

The drawing shows the structure of the proposed device.

The device for monitoring the quality of radiotelephone communication channels contains N channels for processing the input signal, each of which consists of the first counter 2, the AND-NE element 3, the second counter 4, the RS flip-flop 5, the amplitude detector 6, the integrator 7 and the imager 8 pulses , multichannel switch 9, first switch 10, digital-to-analog converter 1 1, N comparators 12 - 2, multichannel adder 13, threshold unit 14, two-threshold comparator 15, first and second keys 16 and 17, reversible counter 18, first inverter 19, third key 20, second in ertor 21, the second commutation torus 22, an OR gate 23, pulse generator 24, the frequency dividing unit 25, an additional multichannel kom32546

background communication channel (CS) at the output

RS flip-flop 5 generates a voltage level equal to either the logical unit level or the logical zero level, respectively. If there are no voice signals in the analyzed QS, then the device selects the QS with the minimum level of output noise. If speech signals appear in one or several QS, then the device selects the QS with the highest output level. After such a choice of COP, its address is determined. 1 il.

mutator 26, N adders 27 - 27, N elements AND 28 - 28, additional element OR 29, decoder 30, first additional counter 31, fourth key 32, buffer register

33, second additional counter

34, an additional frequency division block 35 and a NOT element 36.

The device works as follows.

The input signal (input 1 - input N), which is either a speech signal or noise in the passband of a standard radiotelephone communication channel, is fed to the inputs of drivers 8 of all channels 1 - 1 ", which produce pulses for each positive intersection of the input signal zero lines. The pulses from the output of the imaging unit 8 of the corresponding channel are fed to the input of the first counter 2, which accumulates them for a time determined by the zero-pulse repetition period received to the zeroing input of the counter 2 from the first output of the frequency division unit 25 and having a logic zero level.

In case of overflow of the first counter 2 at time T, where T is the period of zero-zero pulses, the overflow pulse from its output, which has a logic level of zero, enters the input of the AND-NO element 3, which in this case prevents the passage of pulses from the output of block 25 to the input reset the second counter 4.

In the absence of zeroing pulses, the second counter 4 begins to accumulate pulses arriving at its counting input from the second output of block 25 and corresponding to the zeroing cycles. At the same time, the pulses at the second output of the frequency division unit 25 have a delay of 1/8 of the follow-up period relative to the pulses at its first output. If the second counter 4 overflows in time T, equal to the average duration of pauses in the speech signal, then the overflow pulse from the output of counter 4, which has a logic zero level, enters the RS-flip-flop 5 and forms a voltage level at its output .

The above mechanism of the device operation occurs in the case when at the output of the analyzed communication channel (input 1 - input N) there is a voltage consisting only of schum.

When the inputs of the formers 8 of all channels 1–1 are present, they are connected to the combined non-inverting inputs of the adders 27, and their outputs are connected to the non-inverting inputs of all the comparators 12 using the multi-channel switch 9 using the second the switch 22 is connected to the common bus and to the control input

signals, then the average pulse frequency from the output of the imaging unit 8 will not cause the counter 2 to overflow during the time T, while at its output there is a logical unit level. The IS-NE 3 element at the same time permits the passage of pulses from the second output of block 25 to the zeroing input of the second counter 4. from the third key 20 is connected at the same time by the first pulse passing through the output of the first inverter 19. The IS-NOT 3 element to another RS-flip-flop 5 the latter is set to a state in which the level of a logical unit appears at its output.

The algorithm of operation of the device to determine the state of the analyzed communication channels is based on

The voltage from the outputs of the integrators 7 of all channels 1 - 1, for example, positive polarity, is supplied to the inverting inputs of all adders 27, while the output of the adder 27, corresponding to the channel with the minimum output noise level, will have an output voltage that the average frequency of the schum is in positive polarity, but more passable than the standard radioactive level, than the output of the left-channel communication channel by approximately two voltages of other adders 27. Once the average frequency on the combined non-inverted signal in the same band. The inputs of all adders 27 are so, if the output is 50, the voltage of the positive lysed communication channel is present from the output of the digital-analogue

converter 11.

If at some point in time at the inverting inputs of several sums mators 27 there are levels of positive polarity less than the level of positive voltage at the output of the digital-to-analog converter 11, then

there is a speech signal, then at the output of RS-flip-flop 5 there is a logical unit level, and in the case when the output of the analyzed channel contains a voltage consisting only of a sound, then a voltage level appears at the output of the RS-flip-flop 5 equal to the level of logical zero. With

32546

than the logical zero level on the RS-Trigger 5 output appears after a time equal to the filling time of the second counter 4 and is the average of the duration of the pauses of the speech signal T. This is done so that the device does not work for short-term

10 pauses between words, syllables, and voice messages.

If there are no voice signals in the analyzed communication channels, then the logical zero level from the output

15 of the element OR 23 is fed to the control input of the multi-channel switch 9, as well as to the control inputs of the first and second switches 10 and 22. At the same time, the device starts

20 choose a channel with a minimum level of noise.

When a logic zero level arrives at the control input of the second switch 22, the output from the digital converter 25 to the analog converter 11 is fed to the combined non-inverting inputs of the adders 27, and their outputs are connected to the non-inverting inputs of all the comparators using a multichannel switch 9 12 using the second switch 22 are connected to the common bus and to the control input

From the third switch 20, the output of the first inverter 19 is connected.

voltage levels of positive polarity are present, and the outputs of the corresponding comparators 12 are voltage levels equal to the level of the logical unit. Each such level, acting on the corresponding input of the multichannel adder 13, increases the voltage level at its output by the value Di. Thus, the voltage level at the output of the multi-channel adder 13 is determined by the expression: U

ten

the trigger zone of the two-threshold comparator 15, which closes the key 17, and this completes the process of determining the channel with the minimum level of output noise.

If in the selected radiotelephone communication channel the output noise level increases so much that the output voltage of the corresponding adder 27 changes sign to negative, then the output of the corresponding comparator 12 is the output voltage level

miU, where m is the number of channels, in which 15 will take the value of logical zero.

At the same time, at the output of the multi-channel adder, the voltage level 13 will become close to zero and will exit the tolerance zone of the two-threshold comparator

At this time, their output voltage level is less than the voltage level at the output of the digital-analog converter 11.

The voltage from the multichannel output 20–15, the output voltage of which adder 13 simultaneously arrives, opens the second key 17. At the same time, the inputs of the two-threshold comparator 15 and the threshold unit 14. The two-threshold comparator 15 represents

at the level of the output voltage of the multichannel adder 13, equal to Uf jJU, the threshold unit 14

a double comparator with tolerance-25 forms at its output a level of the input signal's area equal to 0.8-1.2 li.

If the voltage at the output of the multi-channel adder 13 is 0.8 4U 7 and 1.2 dU, i.e. out of the tolerance zone of the two-threshold comparator 15, then at the output of the two-threshold comparator 15 a voltage level is formed close to zero, which opens the second key 17, and the control pulses from the output of the generator 24 pass to the inputs of the first and third keys 16 and 20. At the same time, the threshold block 14 with Uj, 7 li, which corresponds to the fact that several comparators 12 have the level of a logical unit at the outputs, forms at its output a level of a logical unit. This level through the inverter 19 and the first switch 10 is supplied to the control input of the third key 20. In this case, the control pulses from the output of the generator 24 through the open second and third keys 17 and 20 of the program zero, which through the first inverter 19 and the first switch 10 are fed to the control input of the third key 20 and the input of the second inverter 21. In this case, the control pulses from the generator output 24 through the open second and first keys 17 and 16 are passed to the input Addition of a reversible counter 18. Each pulse,

35 incoming input Adding reversible counter 18, one step increases the voltage level at the output of the digital-analog converter 11. Increasing the voltage level of 40 at the output of the digital-analog converter 1 1 ultimately leads to the negative voltage of one of the adders 27 the polarity will change to positive, and this will result in the level of a logical unit at the output of the comparator 12 of the corresponding channel, which at the given time has the lowest value of output Subtraction Q reversible running noise.

counter 18, reducing the level of eg - If speech signals appear at one or several of the fringes at the output of the digital-analogue terminal,

then the logical unit level appears at the output of the OR element 23. With eg, the control input of the third key 20 and the input of the second inverter 21 are connected to the output of the threshold unit 14 using the first switch 10, the output of the digital-to-analog converter 11, which lowers the voltage level at the outputs of the adders 27 and leads to the appearance of logical zero levels at the outputs comparators 12. At the same time, the voltage level at the output of the multi-channel adder 13 will discretely decrease

the trigger zone of the two-threshold comparator 15, which closes the key 17, and this completes the process of determining the channel with the minimum level of output noise.

If in the selected radiotelephone communication channel the output noise level increases so much that the output voltage of the corresponding adder 27 changes sign to negative, then the output of the corresponding comparator 12 is the output voltage level

At the same time, at the output of the multi-channel adder, the voltage level 13 will become close to zero and will exit the tolerance zone of the two-threshold comparator

15, the output voltage of which opens the second key 17. At the same time

at the level of the output voltage of the multichannel adder 13, equal to Uf jJU, the threshold unit 14

a zero, which through the first inverter 19 and the first switch 10 is fed to the control input of the third key 20 and to the input of the second inverter 21. In this case, the control pulses from the generator output 24 through the open second and first keys 17 and 16 are passed to the input. reversible counter 18. Every pulse,

input to the input Addition of the reversible counter 18, increases the voltage level at the output of the digital-to-analog converter 11 by one step. Increasing the voltage level at the output of the digital-analog converter 1 1 ultimately leads to the negative polarity of one of the adders 27 will change to positive, and this will lead to the appearance of the level of the logical unit at the output of the comparator 12 of the corresponding channel that has this generator 10 connected to the inverting inputs of the computer rators 12, the outputs of the integrators 7 are connected to the non-inverting inputs of the respective comparators 12, and the non-inverting inputs of the adders 27 are connected to the common switch 22 by means of the second switch 22. Otherwise, the operation of the device at the choice of the communication channel with the highest level of the output signal repeats the operation of the device when selecting a channel with a minimum level of noise. An additional multi-channel switch 26, having two groups of information outputs (output 1 - output N), indicates the selected channel. Thus, after selecting the radiotelephone channel either with the maximum signal level or with the minimum level of noise, the output level of the two-threshold comparator 15 is set units, which enters the zeroing inputs of the first and second additional counters 31 and 34. At the same time, the second additional counter 34 begins to accumulate pulses coming from the output of the dividing unit 35 h Atoty, the period of which corresponds to the selected unit of time. At the same time, the counting input of the first additional counter 31 through the open fourth key 32 receives pulses from the generator 24, while the levels of the logical unit are sequentially formed at the outputs of the decoder 30. When the level of the logical unit at one of the outputs of the decoder 30 coincides with the level of the logical unit at the output of the corresponding comparator 12, then at the output of the element 28 that is connected to the output of the comparator, the level of the logical unit is formed. This logical level through the OR element 29 enters the control input of the fourth key 32 and closes it, while the output of the first additional counter 31 is set to the binary code value corresponding to the address of the selected radiotelephone communication channel. At the same time, from the output of the second additional counter 34, the current value of the duration of the selected channel operation in the binary parallel code goes to the data bus of the buffer register 33, where the logical level also flows

five

0

five

0

five

0

five

ABOUT

five

NIN from the output of the element OR 23, corresponding to the mode of operation of the device. At the same time, from the output of the two-cost comparator 15, the input of the buffer register 33 enters the level of the logical unit, which allows writing to the register 33 of the current information about the operation of the device.

When a signal appears with a maximum level, for example, in another channel, it switches to the channel search mode with the maximum signal level. At the time of the channel search at the output of the two-threshold comparator 15, the logic zero level is set, prohibiting the writing of data to the buffer register 33. At the same time, the logic unit level from the output of the NOT element 36 is fed to the input of the Read register 33, and information is output from it. Then, additional counters 31 and FOR are reset, and the process of determining the channel address is repeated.

Claims (1)

Invention Formula Device quality control diotelephonic communication channels on the author. St. No. 1100737, characterized in that, in order to expand the functionality by determining the address of the selected channel and the duration of its operation, the element NOT, N elements AND, the additional element OR, the fourth key connected in series, the first additional counter and the decoder and serially connected are introduced an additional unit for dividing the frequency; a second additional ToTbij counter and a buffer register; the zero and zero inputs of the first and second additional counters are connected to the output of a two-threshold comparat a, with the entry of the buffer register and the input of the element NOT, the output of which is connected to the read input of the buffer register, the input of the additional frequency divider is connected to the signal input of the fourth key and the output of the pulse generator, the outputs of the decoder through the corresponding elements And, the second inputs of which are connected to the outputs of the corresponding comparators are connected to the corresponding entry of an additional element 91332546JO OR, the output of which is connected to the register, is connected respectively to the equalizing input of the fourth key, with the output of the first additional and second and third inputs of the buffer counter and with the output of the OR element,