JPS5664535A - Coder/decoder monitor circuit - Google Patents
Coder/decoder monitor circuitInfo
- Publication number
- JPS5664535A JPS5664535A JP13988079A JP13988079A JPS5664535A JP S5664535 A JPS5664535 A JP S5664535A JP 13988079 A JP13988079 A JP 13988079A JP 13988079 A JP13988079 A JP 13988079A JP S5664535 A JPS5664535 A JP S5664535A
- Authority
- JP
- Japan
- Prior art keywords
- coder
- alarm
- circuit
- decoder
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Analogue/Digital Conversion (AREA)
- Time-Division Multiplex Systems (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Abstract
PURPOSE:To ensure a monitor for the decoder and coder without giving a decision between the call and noncall, by making use of the information itself passing through both the coder and decoder. CONSTITUTION:The ''1'' or ''0'' is delivered to the terminal 5 when the input signal is decided positive or negative respectively by the circuit 4 which decides the plus and minus of the input signal of a coder. When the input signal is approximate to zero, the ''1'' is delivered to the terminal 6. Then the transmission of alarm is inhibited by the alarm inhibiting circuit 13. At the same time, a compensation is given to the delay between the input and the output of the coder 2 by the delay elements 7 and 8. Thus the circuit 4 detects the coincidence between the plus and the minus of both the input and output signals of the coder 2, and the alarm is transmitted when no coincidence is obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54139880A JPS5931250B2 (en) | 1979-10-31 | 1979-10-31 | Encoder-decoder supervisory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54139880A JPS5931250B2 (en) | 1979-10-31 | 1979-10-31 | Encoder-decoder supervisory circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5664535A true JPS5664535A (en) | 1981-06-01 |
JPS5931250B2 JPS5931250B2 (en) | 1984-08-01 |
Family
ID=15255714
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54139880A Expired JPS5931250B2 (en) | 1979-10-31 | 1979-10-31 | Encoder-decoder supervisory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5931250B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01155719A (en) * | 1987-12-11 | 1989-06-19 | Matsushita Electric Ind Co Ltd | Voice coding and decoding device with monitor function |
-
1979
- 1979-10-31 JP JP54139880A patent/JPS5931250B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01155719A (en) * | 1987-12-11 | 1989-06-19 | Matsushita Electric Ind Co Ltd | Voice coding and decoding device with monitor function |
Also Published As
Publication number | Publication date |
---|---|
JPS5931250B2 (en) | 1984-08-01 |
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