JPS5793734A - Compensation system for signal short break - Google Patents

Compensation system for signal short break

Info

Publication number
JPS5793734A
JPS5793734A JP17036280A JP17036280A JPS5793734A JP S5793734 A JPS5793734 A JP S5793734A JP 17036280 A JP17036280 A JP 17036280A JP 17036280 A JP17036280 A JP 17036280A JP S5793734 A JPS5793734 A JP S5793734A
Authority
JP
Japan
Prior art keywords
short break
signal
inputted
delay circuit
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17036280A
Other languages
Japanese (ja)
Inventor
Shoichi Kurita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17036280A priority Critical patent/JPS5793734A/en
Publication of JPS5793734A publication Critical patent/JPS5793734A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Abstract

PURPOSE:To avoid a rapid status change before and after a signal short break period, by compensating the short break period through the use of a signal received at a specific period just before the short break, if a reception signal is momentarily interrupted. CONSTITUTION:A signal sent from a transmission line 3 is inputted to a reception section directly via switching circuits SW1, SW2, and a part is inputted to a delay circuit 2 and outputted at a terminal (d) after a specified delay time. If short break of a signal is detected at a short break detecting circuit 1, the switching circuits SW1, SW2 are changed over to broken line sides (b), (d). As a result, the input terminal of the delay circuit 2 is connected to an output terminal, the information immediately before the short break stored in the delay circuit is repeated and inputted to a reception section 4. When the short break is restored, the circuits SW1, SW2 are restored to original states (a), (c) for normal signal transmission.
JP17036280A 1980-12-03 1980-12-03 Compensation system for signal short break Pending JPS5793734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17036280A JPS5793734A (en) 1980-12-03 1980-12-03 Compensation system for signal short break

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17036280A JPS5793734A (en) 1980-12-03 1980-12-03 Compensation system for signal short break

Publications (1)

Publication Number Publication Date
JPS5793734A true JPS5793734A (en) 1982-06-10

Family

ID=15903521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17036280A Pending JPS5793734A (en) 1980-12-03 1980-12-03 Compensation system for signal short break

Country Status (1)

Country Link
JP (1) JPS5793734A (en)

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