JPS5928790A - Subscriber circuit of telephone set - Google Patents

Subscriber circuit of telephone set

Info

Publication number
JPS5928790A
JPS5928790A JP13854682A JP13854682A JPS5928790A JP S5928790 A JPS5928790 A JP S5928790A JP 13854682 A JP13854682 A JP 13854682A JP 13854682 A JP13854682 A JP 13854682A JP S5928790 A JPS5928790 A JP S5928790A
Authority
JP
Japan
Prior art keywords
signal
subscriber circuit
counting
processing device
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13854682A
Other languages
Japanese (ja)
Inventor
「ひ」山 邦夫
Kunio Hiyama
Kenji Kawakita
謙二 川北
Michio Suzuki
鈴木 三知男
Osamu Takada
治 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13854682A priority Critical patent/JPS5928790A/en
Publication of JPS5928790A publication Critical patent/JPS5928790A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/32Signalling arrangements; Manipulation of signalling currents using trains of dc pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)

Abstract

PURPOSE:To decrease the load of a processor, by providing a counter counting the change in a line signal in a subscriber circuit and counting the change in the signal with the hardware. CONSTITUTION:A line signal LS is inputted to an FF6 and the output of the FF6 is inputted to an FF7. Logical gates 11, 12 detect that the values of the FFs 6, 7 are the same and an FF8 is operative accordingly. For example, suppose that the period of a clock signal CK is 2ms, when the signal LS within 2ms is changed, the content of the FFs 6, 7 is not the same and no signal is outputted from the gates 11, 12. Thus, even if a short pulse due to the chattering enters the signal LS, it is eliminated. Then, the number of dial pulses is counted by inputting an output of the FF8 to a counter 9. On the other hand, a processor 1 fetches the content of the FF8 and counters 9-1-9-4 by transmitting a specific address to an address bus 2.

Description

【発明の詳細な説明】 本発明は、ダイヤルパルスを計数する電話機の加入者回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a telephone subscriber circuit for counting dial pulses.

この種加入者回路として、従来、第1図に示すように、
処理装置1のプログラムにより、高頻度にライン信号L
Sを監視し、その変化を検出することによシ、ダイヤル
パルスを識別計数するものが知られている。
Conventionally, this type of subscriber circuit is as shown in FIG.
The program of the processing device 1 causes the line signal L to be output frequently.
It is known to identify and count dial pulses by monitoring S and detecting changes therein.

すなわち、電話回線のオンフッタ、オフフッタ信号を′
″0#、′″1#にそれぞれ反映されているライン信号
LS’に処理装置1のプログラムにより直接読み取るた
めに、処理装置1から特定アドレスをアドレスバス2上
に伝送し、それをデコーダ3により受信し、一致が検出
さnると、ゲート4を開き、ライン信号L8’にデー、
タパス5上に送り、処理装置1で読み取るようになって
いる。
In other words, the on-footer and off-footer signals of the telephone line are
In order to directly read the line signal LS' reflected in "0#" and ""1#, respectively, by the program of the processing device 1, a specific address is transmitted from the processing device 1 onto the address bus 2, and it is transmitted by the decoder 3. When a match is detected, gate 4 is opened and data is sent to line signal L8'.
It is sent to the tapas 5 and read by the processing device 1.

しかしながら、このような従来の回路では、ダイヤルパ
ルスは毎秒20パルス以上のものもあり、そのために8
ms位の高頻度で走査をしなければならなかった。その
ために、処理装置の負荷がゴζきくなシ、事実上ダイヤ
ルパルス計数は発呼後のダイヤルを行なう期間しか行な
えなかった。特に、通話中に第3者を呼び出す各種のサ
ービス、また相手話中に遭遇した時の各種のサービス等
を交換機に要求する時、従来はフッキング操作に頼らざ
るを得なかった。このフッキング操作i、o、s〜1秒
位の間、電話機のフックを押すことにより行なわれるが
、これより短い時間だと無視さnるし、艮すぎると切断
となってしまい、ユーザにとって匣いにくい操作となり
、折角の各種のサービスも宝の持ち腐れとなってしまっ
ていた。
However, in such conventional circuits, the dial pulses may be more than 20 pulses per second, so 8
Scanning had to be performed at a high frequency of about ms. Therefore, the load on the processing device is so heavy that dial pulses can actually be counted only during the dialing period after a call is made. In particular, in the past, when requesting various services for calling a third party during a call, or various services for encountering a third party during a call, the user had to rely on hooking operations. This hooking operation is performed by pressing the hook of the phone for about 1 second, but if it is shorter than this, it will be ignored, and if it is too long, it will be disconnected, and it will be a problem for the user. It became difficult to operate, and the various services that had been put in place became useless.

本発明の目的は、M4話機からのダイヤルパルスの計数
全処理装置の負荷を増すことなく実現でき、これにより
、通話中2話中等もダイヤル計数を可能とし、操作誤り
の多かったクツキング操作を不要とし、その代りにダイ
ヤル番号により各種サービスを面接要求することを可能
にする電話機の力目大者回路を提供するものである。
The object of the present invention is to be able to achieve the counting of dial pulses from an M4 phone without increasing the load on the entire processing device, thereby making it possible to count dials even during a call, such as during two conversations, and eliminating the need for picking operations that often result in operational errors. Instead, it provides a powerful telephone circuit that makes it possible to request various services by dialing a number.

このような目的を達成するために、本発明では、加入者
回路内1/C,ライン信号の変化をカウントするカウン
タを設け、信号の変化をハードウェアにより計数するよ
うにしたことに特徴がある。
In order to achieve such an object, the present invention is characterized in that a counter is provided in the subscriber circuit to count the changes in the 1/C and line signals, and the changes in the signals are counted by hardware. .

以下、本発明の実施例を図面により詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.

第2図は本発明による電話機加入者回路の一実施例を示
すもので、6.7はシフトレジスタヲ構成するフリップ
フロップ、8はフリップフロップ、9はカウンタ、10
げゲート、11〜14は論理ゲート、15け読出し/書
込み信号線である。その他の符号は第1図の同じ符号に
対応している。
FIG. 2 shows an embodiment of the telephone subscriber circuit according to the present invention, in which 6.7 is a flip-flop constituting a shift register, 8 is a flip-flop, 9 is a counter, and 10 is a flip-flop.
11 to 14 are logic gates, and 15 read/write signal lines. Other symbols correspond to the same symbols in FIG.

そして、ライン信号L S flシフトレジスタの前段
の7リツプフロツプ6に入力され、そのフリップフロッ
プ6の出力は後段のフリップフロップ7に入力され、こ
のシフトレジスタはクロックCKの立上り信号によりシ
フト動作でれる。
The line signal L S fl is inputted to a seven flip-flop 6 at the front stage of the shift register, and the output of the flip-flop 6 is inputted to a flip-flop 7 at the rear stage, and this shift register can be shifted by the rising edge signal of the clock CK.

論理ゲート11および12ば、フリップフロップ6と7
の値が同じになることを検出しており、そnにより、フ
リップフロップ8を1幼がせている。
Logic gates 11 and 12, flip-flops 6 and 7
It is detected that the values of n become the same, and accordingly, the flip-flop 8 is incremented by one.

例えば、タロツク信号CKの周期が2msであるとすれ
ば、2ms以内のライン信号LSの変化があった場合、
フリップフロップ6と7の値は同じにならず、シタがっ
て、ゲー)11.12からは信号が出ない。そのため、
ライン信号LSの中に、チャツタリング現象による短か
いパルスが入っても、それ全排除することができ、それ
により、誤動作を防止した信号をフリップフロップ8に
反映できる。
For example, if the period of the tarok signal CK is 2ms, if there is a change in the line signal LS within 2ms,
The values of flip-flops 6 and 7 are not the same and are shifted, so no signal is output from gates 11 and 12. Therefore,
Even if a short pulse due to a chattering phenomenon enters the line signal LS, it can be completely eliminated, and thereby a signal that is prevented from malfunctioning can be reflected in the flip-flop 8.

と(に、フリップフロップ8のIPl力を4段からなる
カウンタ9に入力することにより、ライン信号のオフフ
ックへの窯化回数、すなわち、ダイヤルパルスの数ヲカ
ウントすることができる。
By inputting the IPL power of the flip-flop 8 to a four-stage counter 9, it is possible to count the number of times the line signal goes off-hook, that is, the number of dial pulses.

一方、処理装[1でに、アドレスノ(ス2に%定アドレ
スを送ることによりデコーダ3を動作プぜるとともに、
読出し7畳込み信号線15に信号を送る。信号線15が
胱出しを示していれば、論理ゲート13の出力によりゲ
ート10−1〜10−5を開き、フリップフロップ8、
カウンタの各段9−1〜9−4の内容全データバス5を
通して処理装置1に取り込む。
On the other hand, the processing unit 1 operates the decoder 3 by sending a constant address to the address number 2, and
A signal is sent to the read 7 convolution signal line 15. If the signal line 15 indicates bladder evacuation, the output of the logic gate 13 opens the gates 10-1 to 10-5, and the flip-flops 8,
All contents of each stage 9-1 to 9-4 of the counter are taken into the processing device 1 through the data bus 5.

また、信号線15が書込みを示していfば、論理ゲート
14の出力により、カウンタ9の内容はクリアされ、0
が書込まれる。
Furthermore, if the signal line 15 indicates writing, the contents of the counter 9 are cleared by the output of the logic gate 14 and 0.
is written.

上述した本発明により、げ、従来8ms位の周期で処理
装置がライン信号を・胱まなけrLばならなかったのに
対し、約100 m s以上の遅い周期で読めばよく、
処理装置の負荷を大巾に軽減でき、通話中1話中等もダ
イヤル操作によるサービス要求を可能とする。
According to the present invention described above, the processing device only needs to read the line signal at a slow cycle of about 100 ms or more, whereas conventionally the processing device had to read the line signal at a cycle of about 8 ms.
The load on the processing device can be greatly reduced, and service requests can be made by dialing even during a single call.

カウンタの段数ニ、読み出す周期に依存し、必ずしも4
ピツトも必要としない。毎秒20パルス以上の場合でも
、100m5では2パルス程度でありこの場合は高々2
段でよい。
The number of stages of the counter depends on the reading cycle and is not necessarily 4.
No need for a pit. Even in the case of 20 pulses per second or more, at 100 m5 it is about 2 pulses, and in this case, at most 2 pulses.
Steps are fine.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の710人者回路の構成図、第2図は本発
明による加入者回路の構成図である。
FIG. 1 is a block diagram of a conventional 710 subscriber circuit, and FIG. 2 is a block diagram of a subscriber circuit according to the present invention.

Claims (1)

【特許請求の範囲】 1、電話機から送られて来るライン信号を入力する手段
と、該ライン信号のパルスに計数する計数手段と、処理
装置からの指令により、所定の周期で上記計数手段の内
容を読出し、上記処理装置に入力する制御手段とを備え
たことを特徴とする電話機の加入者回路。 2、前記入力手段は、上記ライン信号全所定のタイミン
グでサンプリングする手段と、上記タイミングの時間間
隔内における信号の変化を無視する手段とからなること
を特徴とする特許請求の範囲第1項記載の電話機の加入
者回路。
[Claims] 1. A means for inputting a line signal sent from a telephone, a counting means for counting the pulses of the line signal, and the contents of the counting means at a predetermined period according to a command from a processing device. A subscriber circuit for a telephone set, comprising control means for reading and inputting the information to the processing device. 2. The input means comprises means for sampling all of the line signals at predetermined timings, and means for ignoring changes in the signal within the time intervals of the timings, as set forth in claim 1. telephone subscriber circuit.
JP13854682A 1982-08-11 1982-08-11 Subscriber circuit of telephone set Pending JPS5928790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13854682A JPS5928790A (en) 1982-08-11 1982-08-11 Subscriber circuit of telephone set

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13854682A JPS5928790A (en) 1982-08-11 1982-08-11 Subscriber circuit of telephone set

Publications (1)

Publication Number Publication Date
JPS5928790A true JPS5928790A (en) 1984-02-15

Family

ID=15224674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13854682A Pending JPS5928790A (en) 1982-08-11 1982-08-11 Subscriber circuit of telephone set

Country Status (1)

Country Link
JP (1) JPS5928790A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165953A (en) * 1984-09-08 1986-04-04 Daihatsu Motor Co Ltd Sealing construction of v-belt type non-stage transmission
JPS63177348U (en) * 1987-05-06 1988-11-17

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117393A (en) * 1979-03-02 1980-09-09 Hitachi Ltd Signal processor for subscriber circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117393A (en) * 1979-03-02 1980-09-09 Hitachi Ltd Signal processor for subscriber circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165953A (en) * 1984-09-08 1986-04-04 Daihatsu Motor Co Ltd Sealing construction of v-belt type non-stage transmission
JPS63177348U (en) * 1987-05-06 1988-11-17

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