JP3880230B2 - Dial pulse detection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dial pulse detection circuit for detecting a dial pulse from a DC impulse signal transmitted from a telephone.
[0002]
[Prior art]
Examples of a dial pulse detection circuit for detecting a dial pulse from a DC impulse signal transmitted from a telephone are disclosed in Japanese Patent Application Laid-Open Nos. 59-500842 and 59-28790.
[0003]
A dial pulse detection circuit disclosed in Japanese Patent Application Laid-Open No. 59-500842 is a digital signal processing device for detecting either DTMF or dial pulse from an input signal composed of 16-bit digital data per subscriber, The detection result is composed of a register for serial / parallel conversion and a microcomputer for performing a timing validity checking function for determining whether or not the detected timing is correct.
[0004]
The input signal is composed of digital data of 16 bits per subscriber. The first half 8 bits is a PCM bit including DTMF information, and the second half 8 bits is a dial pulse line signal, which is taken into a buffer with a predetermined clock. Data is extracted from the buffer, the first 8 bits are processed by the DTMF signal processing unit, a wide range of line signals are processed by the dial pulse detection unit, and dial information can be detected from either one.
[0005]
Since the DTMF signal is not directly related to the present invention, a description thereof will be omitted. However, the dial pulse detection unit detects a pulse composed of a transition from an off-hook to an on-hook and an on-hook to an off-hook of the input line signal. It detects the idle state determined by the number and the time when no pulse is detected and the call abandonment determined by the time that the on-hook state lasts.
[0006]
The above detection result is converted into an 8-bit code word, sent to the microcomputer as a parallel signal, the microcomputer determines whether the timing at which the code is input is valid, and sends dial information to the module processor through the read register. To do.
[0007]
A dial pulse detection circuit disclosed in Japanese Patent Application Laid-Open No. 59-28790 includes a shift register that samples a line signal from a telephone at a predetermined timing, a counter that counts the number of dial pulses, and a count value of the counter Is constituted by a processing device for determining the number of pulses and resetting the counter.
[0008]
A line signal from the telephone is sampled at a predetermined clock, and counted in a further counter is number of detected times of change from on-hook to off-hook after the hook changed from off-hook, treat the count result in a predetermined period of approximately 100ms Read into the device.
[0009]
[Problems to be solved by the invention]
By the way, there are basically two types of dial pulse formats, 10pps type and 20pps type, in dial type telephones in Japan.
[0010]
Therefore, in the conventional dial pulse detection circuit described above, the pulse width of the dial pulse is specified, and the dial pulse is determined and detected based on whether or not the pulse width is matched. There is a problem that detection cannot be shared by one circuit.
[0011]
For example, in the dial pulse detection circuit disclosed in Japanese Patent Application Laid-Open No. 59-500842, the input signal is sampled at 4.096 MHz to detect whether 1 bit is high or low, and a change from High → Low → High can be detected. The number of pulses is counted as 1. However, since the input of this detection circuit is provided with a filter so as to exclude pulses with a very short duration, even if Low is detected 1 bit, it is not immediately determined that it has become low, and the maximum of the filter counter It is judged that it became Low only after Low was detected by the number of Bits determined as the value. Accordingly, since the maximum value of the filter counter differs between 10 pps and 20 pps with different pulse widths, two types of dial pulses cannot be shared by one circuit.
[0012]
Further, in the conventional technology, since the detection of the dial pulse is performed by software, the processing is complicated, and further, a control circuit for performing the processing is necessary, and there is a problem that the circuit scale is increased.
[0013]
For example, in the dial pulse detection circuit disclosed in Japanese Patent Laid-Open No. 59-500842, the frequency at which the input signal is sampled and the clock frequency at which the sampling result is digitally processed are different, so a buffer must be provided in the digital signal processing unit. In addition, the processing result is encoded by a microcomputer. A microcomputer also requires a ROM and an operation control circuit necessary for code processing, and the circuit scale becomes very large. One dial pulse detection circuit is required for each subscriber, and the large circuit size is a very big problem in a station that handles many subscribers.
[0014]
Furthermore, in the prior art, since the dial pulse detection is performed by software, the processing is very complicated, so that there is a problem that the software load on the processing unit becomes very heavy.
[0015]
For example, in the dial pulse detection circuit disclosed in Japanese Patent Application Laid-Open No. 59-500842, a complicated process in which a dial pulse detection result is represented in a code word and the timing at which the code is output is determined by a microcomputer. It is configured. In addition, it is necessary to control the operation of the ROM and microcomputer in order to perform these processes, increasing the burden on the software.
[0016]
In the dial pulse detection circuit disclosed in Japanese Patent Application Laid-Open No. 59-28790, the hardware detects only the change in hook of the line signal from High → Low → High and counts the dial. However, this circuit configuration cannot detect between dials, and cannot determine where one dial is finished. Therefore, in order to obtain normal dial information, the software has to perform an addition process after reading the count value, increasing the burden on the software.
[0017]
Therefore, an object of the present invention is to detect a dial pulse from a DC impulse signal sent from a telephone to a telephone line, which can detect either a 10 pps type or a 20 pps type dial pulse type with a single circuit. Is to provide.
[0018]
Still another object of the present invention is to provide a dial pulse detection circuit that can be used in an overseas device that can expand the detection range of the impulse make rate and can cope with countries with different communication standards. It is in.
[0019]
Another object of the present invention is to provide a dial pulse detection circuit that is realized with a simple and small hardware circuit in consideration of the need for a dial pulse detection circuit at a rate of one circuit per subscriber. There is to do.
[0020]
Still another object of the present invention is to provide a dial pulse detection circuit that realizes counting of dial pulses while reducing the burden on software.
[0021]
[Means for Solving the Problems]
In order to solve the above-described problems, a dial pulse detection circuit according to the present invention has the following characteristic configuration.
[0022]
High pulse counter that is enabled when the DC impulse signal sent from the telephone is High and counts the DC impulse signal with a predetermined sampling clock;
And Low Pulse counter the DC impulse signal is enabled when the Low, generates a QA and QB outputs counts the DC impulse signal at a predetermined sampling clock,
A first flip-flop circuit for detecting a hook state based on an output of the High pulse counter;
A second flip-flop circuit for detecting a dial interval based on the output of the High pulse counter and generating a reset signal;
A set-reset flip-flop circuit for detecting a Low pulse area end of the DC impulse signal based on the QA output of the Low pulse counter,
An AND gate for detecting a call from off-hook to on-hook based on the QB output of the Low pulse counter and said first flip-flop circuit,
The output of the set / reset flip-flop circuit is input to a clock terminal, and a counter that counts a dial based on the output of the AND gate;
A latch for holding the dial detected by the counter until the reset signal is generated;
A dial pulse detection circuit comprising:
[0029]
As described above, the dial pulse detection circuit of the present invention counts the low region of the dial pulse that satisfies the predetermined pulse speed and the make rate from the result of sampling the DC impulse signal transmitted from the telephone, using the sampling clock, The dial is detected by counting. Furthermore, by detecting a certain high region, it is possible to detect between the dials, and the dial is detected while reducing the burden of adding the count value by software.
[0030]
The dial pulse is detected by counting the time in the low region of the dial pulse with the sampling clock. For this reason, detection of dial pulses of both the 10 pps type and the 20 pps type can be shared by one circuit.
[0031]
All processing from sampling a DC impulse signal from a telephone to detecting a dial pulse is realized by a simple hardware circuit. For this reason, the circuit scale is small, and the burden on the software of the processing unit is very light.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a preferred embodiment of a dial pulse detection circuit according to the present invention will be described in detail with reference to the drawings.
[0033]
Referring to FIG. 1, according to one embodiment of the present invention, a DC impulse signal sent from a telephone is enabled when it is high, a high pulse counter 1 that counts the DC impulse signal with a sampling clock, and a DC impulse signal when it is low. A low pulse counter 2 that is enabled and counts a DC impulse signal with a sampling clock, a flip-flop circuit F / F3 that detects a hook state, and a flip-flop circuit F / F5 that detects an interval between dials and resets the dial counter , A set / reset flip-flop circuit F / F6 for detecting the end of the low pulse area, an AND gate 4 for detecting a call from off-hook to on-hook, a dial counter 7 for counting the number of low pulses, and a detected dial for CPU It consists of a latch 8 that holds until it clears That.
[0034]
First, the input DC impulse signal will be described with reference to FIG. 2, FIG. 3 and FIG.
[0035]
A DC impulse signal is a signal sent from a telephone when a subscriber uses a dial telephone to make a telephone call. An example is shown in FIG. When the subscriber picks up the handset (off hook), the signal goes high, then when the dial is turned, a Low pulse is sent for the number of dials, and the time between dials until the next dial occurs (minimum) Pause) is High, High during a call after dialing, and Low when the handset is placed (On-hook).
[0036]
There are various standards for this DC impulse signal, and there is a standard that a high pause of 100 ms or more continues as a pre-pause after raising the receiver and a low pause of 110 ms or more after the receiver is placed.
[0037]
There are also standards for the number of dial pulses (hereinafter referred to as dial pulses), the impulse speed indicating the speed of the dial pulse, and the make ratio (High area) indicating the ratio between the High and Low areas. The minimum pause time, which represents the time between dials, varies depending on the dial pulse format of the telephone as shown in FIG. .
[0038]
Here, considering only the low region of the dial pulse, the maximum in the low region is 79.2ms when 9.2pps (10pps-0.8pps formula) / make rate 30% (33% -3%). The minimum is 21.6 pps (20 pps-1.6 pps) / make rate 54% (44% + 10%), and the width is 21.3 ms.
[0039]
Therefore, the low region width of the dial pulse of the input DC impulse signal changes within the range of 21.3 ms to 76.1 ms.
[0040]
Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. 1 and FIGS.
[0041]
First, off-hook and on-hook detection operations will be described.
Referring to the timing chart of FIG. 5, the High pulse counter 1 is enabled when the DC impulse signal is High and starts counting. The clock to be counted is a sampling clock with a period of 5 ms. When 100 ms is counted, a 1-bit wide high pulse is output. When the DC impulse signal is low, the reset state is entered and the output is low.
[0042]
Referring to the timing chart of FIG. 6, the Low pulse counter 2 is enabled when the DC impulse signal is Low and starts counting. The counting clock is a sampling clock with a period of 5 ms, a 1-bit wide High pulse is output to the QA output after 110 ms count, and a 1-bit wide High pulse is output to the QB output after 15 ms count. When the DC impulse signal is high, the reset state is entered, and both the QA and QB outputs output low.
[0043]
F / F3 is an F / F that enables the output of the High pulse counter 1, resets the QA output of the Low pulse counter 2, and uses a sampling clock with a 5 ms cycle as its clock. The output HOOK signal is sent to the CPU processing unit. Sent out. It is assumed that the logic of the HOOK signal transmitted indicates High: off-hook and Low: on-hook state.
[0044]
The F / F 3 operates as shown in the timing chart of FIG. In the initial state, since the high pulse counter 1 outputs low, the HOOK signal also outputs low: on-hook state. When the DC impulse signal becomes High and is counted for 100 ms by the High pulse counter 1, F / F3 is enabled for the first time, and High: Off-hook state is output at the rising edge of the sampling clock. At this time, since the low pulse counter 2 is in the reset state, the output is low. Next, when the DC impulse signal becomes Low and is counted for 110 ms by the Low pulse counter 2, High is input to the reset of F / F3, F / F3 enters the reset state, and Low: on-hook state is output.
[0045]
From the standard of the DC impulse signal, the High region is at the time of pre-pause, dial pulse transmission, minimum pause, and during a subscriber call. The count value of the high pulse counter 1 is set to 100 ms from the standard that the high region at the time of pre-pause is 100 ms or more.
[0046]
Therefore, when the DC impulse signal is at the minimum pause and during a call, the output of the High pulse counter 1 may become High and F / F3 may be enabled. At this time, F / F3 is the rising edge of the sampling clock, and High: off-hook. Output the status. Further, when the dial pulse is transmitted, the output of the High pulse counter 1 becomes Low, and the output of the previous state of High: off-hook state is held.
[0047]
From the standard of the DC impulse signal, the low range is only at the time of dial pulse sending and post pause, and at the time of dial pulse sending, as mentioned above, even if both 10 pps type and 20 pps type are taken into account, 21.3 ms ~ The low pulse in the range of 76.1 ms, and the low pulse of 110 ms or more continues only during post-pause, so the QA output of the low pulse counter 2 uses 110 ms as the count value.
[0048]
Therefore, only when 110 ms is counted by the QA output of the low pulse counter 2, High is input to the reset of the F / F 3, and Low: on-hook state is output. As described above, the operations of the high pulse counter 1, the low pulse counter 2, and the F / F 3, that is, the off-hook and on-hook detection operations, are maintained off-hook even during dial pulses, minimum pauses, and calls after detecting off-hook due to pre-pause. The on-hook state is detected by post-pause, and it can be detected correctly regardless of whether the dial pulse format is 10 pps or 20 pps.
[0049]
Next, the dial pulse counting operation will be described.
Set / Reset F / F6 resets the low pulse counter output QB (hereinafter referred to as R), sets the DC impulse signal (hereinafter referred to as S), uses the sampling clock of 5ms cycle as the clock, and outputs Q as data With the set / reset F / F, the output Q is output to the data input of the own F / F and the clock of the dial counter 7 at the subsequent stage.
[0050]
The operation of the set / reset F / F 6 is as shown in the timing chart of FIG. As an initial state, when S is High and R is Low, the Q output is High regardless of the clock. When a dial pulse is transmitted, S: Low, R: Low, and the data remains High with the previous Q output, so the Q output remains High even when the clock rises. After that, when the DC impulse signal remains in the Low state for 15 ms or longer, High is output to the QB output of Low pulse count 2, and the set / reset F / F6 is in the S: Low, R: High state, Q output goes low. Next, until the DC impulse signal becomes High, the set / reset F / F6 repeats S: Low, R: High, S: Low, R: Low, and the Q output always outputs Low. To do. When the DC impulse signal becomes high, the low pulse count 2 is reset and the QB output is low, the set / reset F / F6 returns to the initial state of S: High, R: Low, and the Q output is High.
[0051]
Therefore, the Q output of set / reset F / F6 changes from Low to High when the DC impulse signal becomes High after Low for 15 ms or more. This means that the rising edge of the low pulse that has been low for 15 ms or longer is detected.
[0052]
F / F 5 is an F / F that outputs the Q pulse output of the High pulse counter 1 after shifting it by 1 bit with a sampling clock having a period of 5 ms.
[0053]
Dial counter 7 enables F / F3 Q output and Low pulse counter 2 QA output inverted by AND gate 4 signal, set / reset F / F6 Q output as clock, F / F5 The output Q is a counter that counts 0 to 0 with reset, and the output is 0 to 4 in 4 bits.
[0054]
The latch 8 is a latch circuit that latches the 4 bits of Q0 to Q3 output of the dial counter 7 with the Q output of the High pulse counter 1 and sends the 4-bit output to the CPU processing unit. The transmitted 4-bit data corresponds to the number of dials as shown in FIG.
The operations of the F / F 5, dial counter 7, latch 8, and AND gate 4 are as shown in FIG. The dial counter 7 starts counting when the AND gate 4 outputs High, that is, when the High of the DC impulse signal continues for 100 ms or more.
[0055]
The count ends when the AND gate 4 outputs Low, that is, when the DC impulse signal Low continues for 110 ms or longer. Counting is performed using the Q output of the set / reset F / F6 as a clock, so the count is performed at the rising edge of the low pulse that continues for 15 ms or more of the DC impulse signal and the count value is output to Q0 to Q3 outputs. In addition, it is reset when the Q output of F / F5 is High, and the Q0 to Q3 outputs all output Low.
[0056]
The data of Q0 to Q3 output from the dial counter 7 is latched by the latch 8, and is latched one bit before the dial counter 7 is reset, and is sent to the CPU processing unit. The CPU processing section reads the latch 8 output asynchronously with the operation of this circuit, and outputs a clear signal for clearing the latch 8 when the latch 8 output is other than all Low. At this time, there is a limit on the reading time of the CPU processing unit, and the dial counter 7 determines the dial and resets once. However, it must be read within 100 ms until resetting is performed again thereafter. Accordingly, if the CPU processing unit reads the latch 8 output at a cycle of less than 100 ms, normal dial information can be read.
[0057]
From the standard of the DC impulse signal, the High region is at the time of pre-pause, dial pulse transmission, minimum pause, and during a subscriber call. The reason why the count value of the high pulse counter 1 is set to 100 ms is as described in the above-described on-hook and off-hook operations. The reason why the output of the high pulse counter 1 is reset to the dial counter 7 is as follows. is there.
[0058]
To reset the pulse counter 7, it is only necessary to detect the minimum pose and detect that the dial has been completed. However, the minimum pose standard is 600 ms or higher for the 10 pps formula, and 450 ms or higher for the 20 pps formula. Since any dial pulse format is longer than 100 ms, even if the output of the High pulse counter 1 is used for resetting the dial counter 7, a minimum pause so-called detection between dials can be performed.
[0059]
The high range when dial pulses are sent is 58.7 ms at maximum when the impulse type is 9.2 pps and the make rate is 54%. Therefore, if the minimum pulse is not sent during dial pulse sending, the dial counter 7 No reset is applied to the dial, and dial-to-dial detection can be performed correctly.
[0060]
The reason for setting the QA output counter value of the low pulse counter 2 to 110 ms from the DC impulse signal standard is as explained in the above-mentioned on-hook and off-hook operations. The 15 ms is as follows.
[0061]
The QB output of the low pulse counter 2 is for detecting the low pulse of the DC impulse signal as described above for the operation. Further, as described in the explanation of the direct current impulse signal, the lowest region of the direct current impulse signal in the low region is 21.3 ms of the dial pulse. However, since the DC impulse signal and the sampling clock with a period of 5 ms are asynchronous signals, it is impossible to know at what timing the low pulses are counted. Therefore, the counter value is set to 15 ms, which is smaller than 21.3 ms, so that the low value of 21.3 ms, which is the minimum value, can be counted no matter what timing the DC impulse signal is input with respect to the sampling clock of 5 ms cycle. (See Figure 10)
[0062]
Therefore, when sampling is performed with a clock having a cycle of 5 ms as in this embodiment, the low region of the DC impulse signal can actually be detected from 20 ms or more.
[0063]
Regarding the period of the sampling clock, the period is not necessarily 5 ms. In the embodiment described above, the sampling clock has been described as 5 ms, but this sampling clock is not limited to the 5 ms cycle. Another 10 ms is possible, and there is no problem as long as it can detect a 21.3 ms low pulse. However, since the DC impulse signal does not change, the finer the sampling, the greater the number of counters, the larger the counter configuration, and the larger the circuit scale. For example, consider the High pulse counter 1 that counts 100 ms. If you use a sampling clock with a 5 ms period, 100/5 = 20 counts. If you use a 1 ms sampling clock, the counter configuration is 100/1 = 100. It is necessary to count, and the counter configuration becomes large.
[0064]
The preferred embodiments of the dial pulse detection circuit of the present invention have been described in detail above. However, the present invention should not be limited only to such embodiments, and various modifications and changes can be made according to specific applications. Of course.
[0065]
【The invention's effect】
As described above, according to the dial pulse detection circuit of the present invention, the following remarkable effects can be obtained.
[0066]
The first effect is that a counter is provided to detect the minimum value in the Low region considering both dial pulse formats, so dial pulse detection of two types of dial pulse formats, 10pps and 20pps, can be performed with a single circuit. Can be shared.
[0067]
The second effect is that the DC impulse signal is logically detected by using a sampling clock to configure a counter, so that the detection unit can be realized by a hardware circuit, and a ROM or microcomputer required for processing by software. Therefore, the circuit scale is small.
[0068]
The third effect is that, after detecting and counting the low pulse of the DC impulse signal, the high region is detected by the counter, and dial information is sent to the processing unit at the end of one dial. It is not necessary to add the information to the incoming information, and the burden on the software can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a dial pulse detection circuit according to the present invention.
FIG. 2 is a diagram showing a DC impulse signal transmitted from a telephone.
FIGS. 3A and 3B are diagrams of a Low region of dial pulses within the standard, where FIG. 3A shows a dial pulse when the Low region is maximum, and FIG. 3B is a diagram showing a dial pulse when the Low region is minimum. is there.
FIG. 4 is a diagram showing a dial pulse standard.
5 is a timing chart of the High pulse counter 1 in the embodiment shown in FIG.
6 is a timing chart of the Low pulse counter 2 in the embodiment shown in FIG.
7 is a timing chart of F / F 3 and off-hook / on-hook detection operations in the embodiment shown in FIG. 1; FIG.
8 is a timing chart of an F / F 6 and low pulse detection operation in the embodiment shown in FIG.
FIG. 9 is a timing chart of a dial count operation.
FIG. 10 is a timing chart of a sampling clock and a DC impulse signal.
FIG. 11 is a diagram illustrating a correspondence relationship between dials.
[Explanation of symbols]
1 High pulse counter 2 Low pulse counter 3 and 5 Flip-flop circuit (F / F)
4 AND gate 6 Set / reset flip-flop circuit (F / F)
7 Dial counter 8 Latch 9, 10 Inverter

Claims (1)

High pulse counter that is enabled when the DC impulse signal sent from the telephone is High and counts the DC impulse signal with a predetermined sampling clock;
And Low Pulse counter the DC impulse signal is enabled when the Low, generates a QA and QB outputs counts the DC impulse signal at a predetermined sampling clock,
A first flip-flop circuit for detecting a hook state based on an output of the High pulse counter;
A second flip-flop circuit for detecting a dial interval based on the output of the High pulse counter and generating a reset signal;
A set-reset flip-flop circuit for detecting a Low pulse area end of the DC impulse signal based on the QA output of the Low pulse counter,
An AND gate for detecting a call from off-hook to on-hook based on the QB output of the Low pulse counter and said first flip-flop circuit,
The output of the set / reset flip-flop circuit is input to a clock terminal, and a counter that counts a dial based on the output of the AND gate;
A latch for holding the dial detected by the counter until the reset signal is generated;
A dial pulse detection circuit comprising:

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