JPS5925425A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor circuit having a high-speed operation with small power consumption and high density of integration, by connecting an enhancement type FET which receives application of clock at its gate in series to an enhancement-depletion type inverter. CONSTITUTION:A clock pulse phi1 is applied to a gate electrode 17 of an enhancement type IGFETQ6. The FETQ6 conducts when the pulse phi1 is negative. Therefore, an outut signal is extracted from a drain 19 of an FETQ7 when a signal is supplied to a terminal 20. When the pulse phi1 is zero, the FETQ6 becomes nonconductive. Thus no current flows to the semiconductor circuit to ensure small power consumption. At the same time, it is possible to keep a high- speed performance of an enhancement-depletion type inverter circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor circuit, and particularly to a clocked gate semiconductor circuit using an enhancement type insulated gate field effect transistor (hereinafter referred to as an IGFET) and a debt gate type IGFET.

In order to reduce power consumption, enhancement type IGFETs and circuits have been conventionally used, and furthermore, enhancement and deblessing circuits have been conventionally used to increase switching speed. . 'Figure 1 shows a clocked gate inverter circuit using a kP channel enhancement type IGFET. Enhancement type I G F E
Drain 1 of T Q I is connected to constant power supply vDDK,
IGFETQ.

A lock pulse f is applied to the gate 2 of the IGFETQI as shown in FIG. 2, for example, and the source 3 of the IGFETQI is connected to the drain 4 of the enhancement type IGFETQm and at the same time serves as an output terminal. Further IG
The gate electrode 5 of FETQ is used as an input terminal,
The source 6 of IcFETQ is connected to ground potential (OV). IGF when clock pulse f is -17V
Since ETQ+ becomes conductive, IGFETQs is connected to the input.
When a voltage whose absolute value is higher than the threshold voltage (for example, −2.0×) is applied to the IGFETQ.

Current flows in the direction from the source 6 of IGFETQ to the drain 1 of IGFETQ, but when the clock pulse f is 0■, I
Since G F E T Q l becomes non-conductive,
No current flows. Therefore, in a clocked gate device that is used by applying a clock to the gate of load transistor Q, the power consumption is as follows:
The time the TV is turned on)/(the period of locking) decreases significantly. However, this enhancement W, IG
In a clocked gate device using FET, IGFE
The channel length of TQ is 3, the channel width is W, and the channel length of IGFETQ is L! , the channel width is W! In order to perform normal inverter operation when MI I GF
Since ETQ+ is used as a load transistor, the switching speed is not very fast.

On the other hand, FIG. 3 shows an enhancement-depression type inverter circuit that has not been used in the past. The drain 7 of the depletion enhancement type IGFETQs is connected to a constant power supply V, and the gate electrode D8 and source 9 of the IGFETQs are connected to the enhancement type IGFETQ.
It is connected to the drain 10 of 4 and serves as an output terminal. Furthermore, the gate electrode 11 of the IGFET Q 4 is an input terminal, and the source 12 is at ground potential. In the case of the configuration shown in Figure 3, IGFETQs
Since it is a depressurized type, the switching speed is approximately 1.5 to 2 times faster than the configuration shown in Fig. 1, and the channel length of IGFETQs is Ls, the channel width is W, and the channel length of IGFETQ4 is L4
, when the channel width is W4, I G F E
If the threshold voltage of T Q s is set to an appropriate value, (W4@
L%)/(ws-L4)=about 3, which is advantageous in terms of area since it can be much smaller than the configuration shown in FIG. However, when a signal that makes the input KIGFET Q conductive is applied, current always flows, so the configuration shown in Figure 3 has the disadvantage of higher power consumption than the configuration shown in Figure 1. be.

An object of the present invention is to provide a semiconductor device including an IGFET with high switching speed, low power consumption, and high integration density. The present invention is characterized in that an enhancement type IGFET whose gate is connected to a clock pulse source is connected in series to a conventional circuit as shown in FIG.

According to the present invention, there is provided a first insulated gate field effect transistor of a deblessing quadruple type whose gate and source are commonly connected, and a conduction resistance smaller than the resistance when the first transistor is conductive, and responsive to a clock pulse. a series circuit consisting of a second enhancement type insulated gate field effect transistor which periodically conducts as shown in FIG. A semiconductor circuit includes means for connecting a third transistor in series between Tfl, an output terminal, and means for connecting the output terminal to an intermediate connection point between the third transistor and the series circuit. can get.

In the present invention, since the conduction resistance of the second transistor is made smaller than that of the first transistor, high-speed operation can be realized.

The present invention will be explained below using the drawings. FIG. 4 is a diagram showing an embodiment of the present invention, in which the drain 13 of a depletion type IGFETQI is connected to a constant power source V, the gate electrode 14 and source 15 are connected to the drain 16 of an enhancement type IGFgTQs, and the source 1
8 is an enhancement type IGFETQ, ? drain 1
9 and serves as an output terminal. Also IGF
A clock pulse f is applied to the gate electrode 17 of E T Q a.
, and the gate electrode 20 of IGFKTQ serves as an input terminal. In this configuration, the clock pulse fI is a lock pulse of 5 as shown in FIG. 2, so in terms of power consumption it is equivalent to the conventional clocked gate configuration shown in FIG. 1, and the amplitude of the clock pulse /, is large・
Since the resistance of I G F E T Q @ in the conductive state is negligible compared to the resistance of I G F E T Qs, the switching speed is also the same as that of the configuration shown in Fig. 3. The speed is equivalent to the switching speed. That is, the present invention has both the advantage of low power consumption of the conventional configuration shown in FIG. 1 and the advantage of high switching speed of the conventional configuration of FIG.

Furthermore, regarding the area occupied on the semiconductor substrate in the configuration of the present invention, since I G FET Q * may be an FET of the minimum size in the process, it is hardly thicker than in the configuration shown in FIG. 3. It has the advantage of being much smaller than the configuration shown in FIG.

For example, if it is possible to flow current to the clock pulse generator, the drain 1 of IGFETQ in FIG.
If the power supply connected to 3 is set to 3, it is possible to reduce the occupied area compared to the structure of a power supply with only 1 p-pulse f.

FIG. 5 shows an embodiment of a delayed dynamic flip-flop. The enhancement type IGFET Qss is a transfer gate for reading and holding input data, and the enhancement type IGFET Qt 4 is also a transfer gate for reading and holding data. The circuit of the present invention includes an inverter T consisting of a depletion type IGFETQI and two enhancement type IGFETs Qe and Qre, a depletion type IGFETQ+, and an enhancement type IG
Inverter Tw consisting of FETQrt
Output is coming out from the drain of OIGFETQ. Kutsk Pulse/, and f! has a waveform as shown in FIG. In FIG. 5, the first input signal is read out as an output at the timing of the input signal f, which is read at the timing of /.

Also, in the configuration of the present invention (FIG. 4), the transistor Q,
It goes without saying that even if the positional relationship with transistor Q6 is reversed KL', the same effect as in the configuration shown in FIG. 4 can be obtained.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a clocked gate using a conventional enhancement type IGFET, Figure 2 is a diagram showing the waveform of the clock pulse f used in Figure 1, and Figure 3 is a circuit diagram of a clocked gate using a conventional enhancement type IGFET. 4 is a circuit diagram of a depreciation type inverter, FIG. 4 is a diagram showing the basic configuration of the present invention, FIG. 5 is a diagram showing an applied example using the present invention, and FIG.
The clock pulses /+ and f also used in the circuit shown in the figure. FIG. In the figure, Q is a depression type IGFET. Q and Q are enhancement type IGFETs, Q. are depressive type IGFETs, Q, and Q. is the enhancement 'MI IGFET, If l and f! indicates Kutsk pulse, ■ indicates power supply. D ￥l eye tea 2nd rod 3 eye tea 4 eye rod 5 eye 6th eye

Claims (1)

[Claims] a field-effect transistor whose gate and source are commonly connected; Periodically conductive enhancer) W's second +E [gate field-effect transistor to lj series circuit and to the gate! lK! a third insulated gate field effect transistor of the Bonnnont type to which the first physical signal is supplied; means for connecting the series circuit and the third transistor in series to a source iMI; an output terminal; A semiconductor circuit characterized by further comprising: means for connecting the output device to an intermediate connection point between the third transistor and the series circuit.