JPS5925243A - Dicing method - Google Patents

Dicing method

Info

Publication number
JPS5925243A
JPS5925243A JP57133716A JP13371682A JPS5925243A JP S5925243 A JPS5925243 A JP S5925243A JP 57133716 A JP57133716 A JP 57133716A JP 13371682 A JP13371682 A JP 13371682A JP S5925243 A JPS5925243 A JP S5925243A
Authority
JP
Japan
Prior art keywords
dicing
wafer
conductive
static electricity
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57133716A
Other languages
Japanese (ja)
Inventor
Takashi Miwa
孝志 三輪
Tamotsu Usami
保 宇佐美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57133716A priority Critical patent/JPS5925243A/en
Publication of JPS5925243A publication Critical patent/JPS5925243A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To make static electricity generated during dicing release to the outside, and to dice a wafer so as not to generate the electrostatic breakdown of the circuit element of the wafer by fixing the wafer onto a conductive fixing means grounded and dicing the wafer. CONSTITUTION:The wafer to be diced 1 is fixed onto a conductive substrate 3 by conductive adhesives 2 under the state in which a circuit pattern is formed. The base material 3 is connected onto a conductive dicing table 4 in a conductible shape, and the table 4 is grounded by a ground wire 5. Consequently, even when static electricity is generated during the dicing of the wafer 1, static electricity is not stored in the wafer 1 because it is guided to the outside through the conductive adhesive 2, the conductive base material 3, the dicing table 4 and the ground wire 5 from the wafer 1 and escapes. Accordingly, the generation of the electrostatic breakdown of the circuit element of a pellet due to static electricity generated in the wafer 1 can be prevented.

Description

【発明の詳細な説明】 本発明はウェハのダイシング方7ノソ、!侍に、回路の
静市、破壊を起こすことなくウェハをダ・イシングゴる
ことができるダイシング方法に関する。
[Detailed Description of the Invention] The present invention provides 7 ways to dice wafers! This paper relates to a dicing method that allows wafers to be diced without destroying circuits.

一般に、半導体製品の製造過程においてウェハのダイシ
ングを行な5項合、ダイシング時に発生−4−ろ訃亀気
により回路素子が静電破壊をひき起こすことがあり、特
K M OS型製品ではこの危険性が太きい。
Generally, when dicing wafers in the manufacturing process of semiconductor products, electrostatic damage to circuit elements may occur due to the cracking generated during dicing. The danger is great.

そこで、(IY−米の、回路素子の静電破壊を防止す6
7、’= メ、r) エハヲ金、9.i 3%9のダイ
シングデープルにfl+V ’L、該ダイシングテーブ
ルを接lj14 シた状態でハーフカフ)クィソングを
行なった後、ウェハをクラソギングシ−,てペレットに
分割している。しかし、この方式では、ダイシングがハ
ーフカットダイシングであるので、その後のクラツキン
グが要求される上に、クラッキング時の欠り゛不良やウ
ェハ屑の伺着によるベレットの表面傷等の不良が発生す
るおそれがある。
Therefore, (IY-U.S.) 6.
7,' = Me, r) Ehawokin, 9. After performing a half-cuff quisong with the dicing table in contact with the dicing dimple of i3%9, the wafer is divided into pellets by crassoging. However, since this method uses half-cut dicing, subsequent cracking is required, and there is a risk of defects such as chipping during cracking or surface scratches on the pellet due to wafer debris adhering. There is.

一方、ベレントザイズの縮小、ベレットアドレス保持等
の必要付から、ウェス・をフルカットダイシング′fろ
ことか考えられている。ところが、フルカットダイシン
グでは、ダイシング後にベレットがばらばらKならない
ように粘着テープ等の固定イオ料でウェス・を予め固定
しておく必要がある。
On the other hand, due to the necessity of reducing the pellet size and maintaining the pellet address, full-cut dicing of the rag is being considered. However, in full-cut dicing, it is necessary to fix the rag in advance with a fixed ion material such as adhesive tape to prevent the pellet from falling apart after dicing.

そのため、ダイシング中はウェス・のアースをとること
が難しく、ダイシング中に発生ずる静電気により回路素
子の静電、破壊が起こり易いという問題がある。
Therefore, it is difficult to ground the rag during dicing, and there is a problem in that the static electricity generated during dicing tends to cause static electricity and damage to the circuit elements.

したがって、本発明の目的は、ダイシング中に発生する
静電気を夕[部に逃がし、ウェス・(またはベレット)
の回路素子の静電破壊を起こすことなくダイシングでき
ろダイシング方法を袂供することにある。
Therefore, an object of the present invention is to release the static electricity generated during dicing to the waste cloth (or pellet).
An object of the present invention is to provide a dicing method that can perform dicing without causing electrostatic damage to circuit elements.

以下、本発明を図面に示すツ!、施例にしたがって詳細
に説明する。
Hereinafter, the present invention will be illustrated in the drawings. , will be explained in detail according to examples.

第1図は本発明によるダイシング方法の一実施例を示す
ダイシング機構の概略的断面図である。
FIG. 1 is a schematic cross-sectional view of a dicing mechanism showing an embodiment of the dicing method according to the present invention.

この実施例において、ダイシングされるウェハ1は回路
バクーンを形成された状態で導電性接着剤2により導市
性基月3の上に固定されている。
In this embodiment, a wafer 1 to be diced is fixed on a conductive substrate 3 with a conductive adhesive 2 with a circuit board formed thereon.

導7毬憔接着剤2と導電付基」」3はたどえば通常の粘
着テープの如く予め導りu伯::X月;(の十に導電性
接着剤2を伺着させ、その上にウェハJを粘着さぜるも
のでもよい。
7. Adhesive adhesive 2 and conductive base 3. Adhere the conductive adhesive 2 to the adhesive tape 3 in advance like a normal adhesive tape, and then apply the conductive adhesive 2 to the The wafer J may also be glued to the surface.

前記導電性基月3は導115.性を持つダイシングテー
ブル4の上に導電可能に接続、゛)れ“(いる。このダ
イシングテーブル4はアース線5により接地されて見・
る。
The conductive base 3 is conductive 115. The dicing table 4 is electrically conductively connected to the top of the dicing table 4, which has a
Ru.

したがって、本実施例においては、ウェハ1は導電付接
着剤2.導電性シ1(月3.ダイシングデープル4.ア
ース線5を介して接地されていることになる。
Therefore, in this embodiment, the wafer 1 is coated with the conductive adhesive 2. It is grounded via the conductive wire 1 (moon 3, dicing dimple 4, and ground wire 5).

本実施例においてウェハjを図示しないダイザ−でダイ
シングする場合、ダイシング中にウェハ1に静匍、気が
発生しても、その静to、 p(c*:ウェス・1から
導電性接着剤2.導電性基月3.ダイ・/ングテープル
4.アースI%!5を経て外部に導びかれて逃げるので
、ウェハ1に蓄積されることがない。
In this embodiment, when the wafer j is diced with a dizer (not shown), even if static electricity is generated on the wafer 1 during dicing, the static to, p(c*: from the rag 1 to the conductive adhesive 2 Since it is led to the outside through the conductive substrate 3. the die/dying table 4. the ground I%!5 and escapes, it does not accumulate on the wafer 1.

その結果、本実施例眞よれば、ダイシング中にウェハ1
に発生する静電気によりベレットの回路素子の静電破壊
をひき起こすことを防止することができる。
As a result, according to this embodiment, the wafer 1 during dicing
It is possible to prevent electrostatic damage to the circuit elements of the pellet due to the static electricity generated.

この実施例はウェハ1のダイシング、特にハーフカット
ダイシングに比べてアースをとりにく(・フルカットダ
イシングにおける回路素子の静電破壊の防IJ二に有効
である。
This embodiment is effective in dicing the wafer 1, especially in preventing electrostatic damage to circuit elements during full-cut dicing.

?P、2図は本発明によるダイ・/ング方法の第2実施
例を示すダイシング機構の概略的説明図である。
? FIG. 2 is a schematic explanatory diagram of a dicing mechanism showing a second embodiment of the die/dicing method according to the present invention.

この実施例においては、アース線5はダイシングテーブ
ル4ではなくて、導電件基拐3からi面接アースをとる
よう該導電牲糸拐3に接続されている。
In this embodiment, the ground wire 5 is not connected to the dicing table 4, but is connected to the conductive thread 3 so as to provide an i-plane ground from the conductive thread 3.

したがって、この実施例では、ウェハ1に発生した静電
1気は導電付接着剤2.導筒、性基イ;13からアース
線5を経て速やかに接地に逃がされろ。
Therefore, in this embodiment, the static electricity generated on the wafer 1 is removed by the conductive adhesive 2. Conduit, base A: Immediately escape from 13 to ground via ground wire 5.

また、アース線5は場合にJ:っては導電性接着剤2に
直接接続し、ウェハ1に発生したn電見をウェハ1から
導電性接着剤2.アース線5を経て接地に導ひいてもよ
い。
In addition, the ground wire 5 is directly connected to the conductive adhesive 2 in the case, and the electrical current generated on the wafer 1 is transferred from the wafer 1 to the conductive adhesive 2. It may be led to the ground via the ground wire 5.

さらに、第3図に示すように、ウェハ1をダイシングテ
ーブル4の土にIM接導TK、 ?8J能に固定し、該
ダイシングテーブル4に接続したアース線5によりウェ
ハ1の静電気を外部に速やかに放出するようにしてもよ
い。
Furthermore, as shown in FIG. The wafer 1 may be fixed at a power of 8 J, and the static electricity of the wafer 1 may be quickly discharged to the outside through the ground wire 5 connected to the dicing table 4.

なお、本発明はフルカットダイシングに特にイイ利であ
るが、ハーフカットダイシングにも適用できろ。
Although the present invention is particularly advantageous for full-cut dicing, it can also be applied to half-cut dicing.

以上説明したように、本発明によれば、ダイシング中に
発生する静電気がウェハに蓄積されずに外部に放出され
るので、静■、気によるウェハ(ベレット)の1ijJ
路素子の破壊を防止ずろことができる。
As explained above, according to the present invention, the static electricity generated during dicing is not accumulated on the wafer and is discharged to the outside, so that the wafer (bullet) is not damaged by static electricity or air.
This can prevent damage to the circuit elements.

QWに、本発明をフルカットダイシングに適用すしば、
クラッキングが不要となる」二に、クラッキングに伴な
う欠は不良やウェハ屑によるベレノトの表面傷の発/j
′−,笠を排除でき、さらにペレノトザイズの縮小やベ
レットアドレスの保持も可能となる。
If the present invention is applied to full cut dicing for QW,
Cracking is not necessary.''Secondly, cracking causes defects and wafer debris to cause surface scratches on the berenoto.
′-, the cap can be eliminated, and it is also possible to reduce the pellet size and maintain the pellet address.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるダイシング方法の一実施例を示す
ダイシング機構の概略的断面図、第2図は本発明による
ダイシング方法の他の1つの実施例を示すダイシング機
構の概略的断面図、第3図は本発明のダイシング方法の
さらに他の実施例を示すダイシング機構の概略的断面図
である。 1・・・ウェハ、2・・・導筒、廿接着剤、3・・導電
件基利、4・・ダイシングテーブル、5・・・アース線
。 代理人 弁理士  薄 1)利 卒− ′、り 第  1  図 第  2  図 / 第  3  図 メ グ 1
FIG. 1 is a schematic cross-sectional view of a dicing mechanism showing one embodiment of the dicing method according to the present invention, and FIG. 2 is a schematic cross-sectional view of a dicing mechanism showing another embodiment of the dicing method according to the present invention. FIG. 3 is a schematic cross-sectional view of a dicing mechanism showing still another embodiment of the dicing method of the present invention. DESCRIPTION OF SYMBOLS 1...Wafer, 2...Conductor, adhesive, 3...Conductor material, 4...Dicing table, 5...Ground wire. Agent Patent Attorney Susuki 1) Li Graduation - ', Figure 1 Figure 2 / Figure 3 Meg 1

Claims (1)

【特許請求の範囲】 1 ウェハのダイシング方法において、ウェハを、接地
された導1ハ1性の固定手段上に固定してダイシングを
行なうことを特徴とするダイシング方法。 2、固定手段が、ウェハな導電付接着剤で固定する導電
恰基月および該導電件基利を導1℃oJ能に固定−イー
るf!電牲のダイシングテーブルよりなり、核ダイシン
グテーブルが接地されていることを特徴とする特rγI
:箱求の範囲第1項記載のダイシング方法。 3 固定手段が、ウニ・・を導′frL性接着剤でし1
定する導電性基セおよび該導電性基利な導電b]能に固
定するダイシングテーブルよりなり、前記導電性ノN+
イが接地されていることを特徴とするl持W)請求の峠
囲第1項記載のダイシング方法。 4 固定手段が導筒、牲のグイソングテーブルよりなり
、該ダイシングテーブルが接地されていることを特許と
するIr、〒¥「請求の範囲第1項記111yのクーイ
シング方法。 5、 ウェハをフルカットダイシング−「ろことな特徴
どする特■′「請求の範囲第1項フ、(゛いし2第4項
のいずれかに記載のダイシング方法・
[Scope of Claims] 1. A dicing method for wafers, characterized in that dicing is carried out by fixing the wafer on a grounded conductive fixing means. 2. The fixing means fixes the conductive base using a conductive adhesive such as a wafer, and fixes the conductive base at a temperature of 1°C. A special rγI consisting of an electrolytic dicing table, characterized in that the nuclear dicing table is grounded.
: The dicing method described in item 1 of the scope of the box test. 3 The fixing means is a sea urchin...
and a dicing table that fixes the conductive base to a conductive base;
1. The dicing method according to claim 1, characterized in that (i) and (b) are grounded. 4. The dicing method according to claim 1, item 111y, patented in that the fixing means consists of a conduit and a sacrificial dicing table, and the dicing table is grounded. 5. The dicing method according to claim 1. Cut dicing - "The dicing method according to any one of claims 1, 2, 4, etc."
JP57133716A 1982-08-02 1982-08-02 Dicing method Pending JPS5925243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57133716A JPS5925243A (en) 1982-08-02 1982-08-02 Dicing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57133716A JPS5925243A (en) 1982-08-02 1982-08-02 Dicing method

Publications (1)

Publication Number Publication Date
JPS5925243A true JPS5925243A (en) 1984-02-09

Family

ID=15111228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57133716A Pending JPS5925243A (en) 1982-08-02 1982-08-02 Dicing method

Country Status (1)

Country Link
JP (1) JPS5925243A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190351U (en) * 1986-05-22 1987-12-03
JPS62190352U (en) * 1986-05-22 1987-12-03

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62190351U (en) * 1986-05-22 1987-12-03
JPS62190352U (en) * 1986-05-22 1987-12-03

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