JPS6242540Y2 - - Google Patents
Info
- Publication number
- JPS6242540Y2 JPS6242540Y2 JP1980148228U JP14822880U JPS6242540Y2 JP S6242540 Y2 JPS6242540 Y2 JP S6242540Y2 JP 1980148228 U JP1980148228 U JP 1980148228U JP 14822880 U JP14822880 U JP 14822880U JP S6242540 Y2 JPS6242540 Y2 JP S6242540Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electronic circuit
- circuit device
- connection
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 17
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案は、電子回路装置に関するものであり、
特に半導体装置等の電子回路装置を輸送、調整す
る際に静電気などによる高電圧によつて電子回路
装置が破壊、損傷されることを防止するものであ
る。[Detailed description of the invention] The present invention relates to an electronic circuit device,
Particularly, when transporting or adjusting electronic circuit devices such as semiconductor devices, it is intended to prevent the electronic circuit devices from being destroyed or damaged by high voltage caused by static electricity or the like.
従来より電子回路装置、特に半導体装置は、静
電気などによつて、損傷を受けることが知られて
おり、この損傷を防止するために、端子間に高電
圧を逃がすための余分な回路を組み込んだり、
又、導電性のスポンジなどに半導体装置を差し込
んで取り扱うなどの工夫がなされている。しか
し、前者の場合は余分な回路を付加するため特性
劣化や不良が生じやすく、コストが高くなり、後
者の場合は、いつたん導電性スポンジから取りは
ずすと損傷を防止できないという難点があつた。 It has long been known that electronic circuit devices, especially semiconductor devices, can be damaged by static electricity, etc. In order to prevent this damage, extra circuits are built in to release high voltage between terminals. ,
In addition, efforts have been made to handle the semiconductor device by inserting it into a conductive sponge or the like. However, in the former case, extra circuits are added, which tends to cause characteristic deterioration and defects, which increases costs, and in the latter case, there is a problem that damage cannot be prevented once removed from the conductive sponge.
本考案は、前記従来の欠点をなくす電子回路装
置を提供するものである。 The present invention provides an electronic circuit device that eliminates the above-mentioned conventional drawbacks.
本考案は、基本的には、電気的に保護すべき電
子回路装置の端子間を電気的に接続して一点に集
めるものであり、静電気や事故による高電圧がこ
の点を通過するようにして損傷を防止するもので
ある。 This invention basically connects the terminals of electronic circuit devices that should be electrically protected and collects them at one point, so that high voltage caused by static electricity or accidents passes through this point. This is to prevent damage.
さらに電子回路装置の使用にあたつては、電気
的に接続した箇所を除去することによつて、電子
回路装置を正常に使用できるようにするものであ
る。 Further, when using the electronic circuit device, the electrically connected portions are removed so that the electronic circuit device can be used normally.
第1図a,bは本考案の第1の実施例における
電子回路装置を示すものである。同図に於て第1
図aは側面断面図、第1図bは下面図を示してお
り、1はICチツプを保持する絶縁基板、2はリ
ードピン、3はICチツプ、4はリードピン2と
ICチツプ3のパツドとを接続するワイヤーリー
ド、5はICチツプ3を保護する保護カバー、6
は本考案に係る結線で、リードピン2に電気的に
接続されている。7は結線6の接続部、8は基板
1の切断部である。本実施例に示す如く、本電子
回路装置を使用する時、例えば、本電子回路装置
をICソケツト等に挿入した後、切断部8を切り
落すことによつて、接続部7を除去する。この様
にして各リードピン2はそれぞれ電気的に分離さ
れ使用可能状態となる。ここで絶縁基板1がプリ
ント基板やアルミナ基板であるときは、浅い切り
目を設けておくことにより絶縁基板1を切断部8
で容易に切り落すことが出来る。 FIGS. 1a and 1b show an electronic circuit device according to a first embodiment of the present invention. In the same figure, the first
Figure a shows a side sectional view, and Figure 1 b shows a bottom view, where 1 is an insulating substrate holding an IC chip, 2 is a lead pin, 3 is an IC chip, and 4 is a lead pin 2.
A wire lead connects to the pad of IC chip 3, 5 is a protective cover that protects IC chip 3, 6
is a connection according to the present invention, and is electrically connected to the lead pin 2. Reference numeral 7 indicates a connecting portion of the wire connection 6, and reference numeral 8 indicates a cutting portion of the substrate 1. As shown in this embodiment, when using the present electronic circuit device, for example, after inserting the present electronic circuit device into an IC socket or the like, the connecting portion 7 is removed by cutting off the cutting portion 8. In this way, each lead pin 2 is electrically isolated from each other and becomes ready for use. When the insulating substrate 1 is a printed circuit board or an alumina substrate, a shallow cut is made to cut the insulating substrate 1 into the cut portion 8.
It can be easily cut off.
結線6は蒸着、印刷等の一般的方法によつて容
易に形成出来る。また本実施例では結線6を露出
する構成としているが、絶縁基板1内部に埋込む
様な構成にしても良いことはもちろんである。さ
らに蒸着、印刷等したものを、はぎとり又は、こ
すりとることによつても達成できる。 The wire connection 6 can be easily formed by a common method such as vapor deposition or printing. Further, in this embodiment, the connection wire 6 is exposed, but it is of course possible to embed it inside the insulating substrate 1. Furthermore, it can also be achieved by peeling off or rubbing off the deposited or printed material.
第2図は本考案の第2の実施例における電子回
路装置の下面図を示すもので、結線の接続部のみ
を外部に露出させていることを特徴としている。
すなわち同図において、11は絶縁基板、12は
リードピン、13は各リードピンを接続する結線
で、絶縁基板11に埋込まれている。14は絶縁
基板11の開孔部15に設けられた結線13の接
続部である。 FIG. 2 shows a bottom view of an electronic circuit device according to a second embodiment of the present invention, which is characterized in that only the connection portions of the wires are exposed to the outside.
That is, in the figure, 11 is an insulating substrate, 12 is a lead pin, and 13 is a connection for connecting each lead pin, which is embedded in the insulating substrate 11. Reference numeral 14 denotes a connecting portion of the wire 13 provided in the opening 15 of the insulating substrate 11.
第2図に示すように本実施例では外部に露出せ
しめた開口部15に、レーザーなどを照射して結
線の接続部を焼き切る。 As shown in FIG. 2, in this embodiment, the opening 15 exposed to the outside is irradiated with a laser or the like to burn out the connection portion of the wire.
レーザーを用いる場合、開孔部15には透明膜
が設けられていてもよく、又、電子回路装置の基
板11の内部深くにあつても差し支えない。 When a laser is used, the aperture 15 may be provided with a transparent film, or may be located deep inside the substrate 11 of the electronic circuit device.
また、本実施例では結線13を1ケ所に集めて
接続部14を設けているが、開孔部15に導電シ
ール等を接着し、必要に応じてこの導電シールを
はがして電子回路装置を使用する様にしても良
い。このようにした場合には、電子回路装置の実
装着直前などのテストの際に導電シールをはがし
て行ない、テスト後、不良品のみに該シールを添
付し直すなどの一回の単純操作によつて回路のテ
ストや良品、不良品の判別が合理的に行ないうる
特徴もある。 In addition, in this embodiment, the connections 13 are gathered in one place to provide the connection part 14, but a conductive seal or the like is adhered to the opening part 15, and the conductive seal is peeled off as necessary to use the electronic circuit device. You can do it as you like. In this case, a simple operation such as peeling off the conductive seal during the test immediately before mounting the electronic circuit device, and reattaching the seal only to the defective product after the test is performed. It also has the advantage of making it possible to conduct circuit tests and distinguish between good and defective products in a reasonable manner.
以上の様に、本考案によれば、電子回路装置を
機器に装着した後、機器の使用直前に保護機能を
取り去れる簡便な機能を提供出来るので利用価値
が高い。 As described above, the present invention has high utility value because it can provide a simple function that allows the protection function to be removed immediately after the electronic circuit device is installed in the device and immediately before the device is used.
第1図a,bはそれぞれ本考案の第1の実施例
における電子回路装置の側面断面図および下面
図、第2図は本考案の第2の実施例における電子
回路装置の下面図である。
1,11……基板(絶縁基板)、2,12……
外部リード端子(リードピン)、3……回路素子
(ICチツプ)、6,13……結線。
1A and 1B are a side sectional view and a bottom view of an electronic circuit device according to a first embodiment of the present invention, respectively, and FIG. 2 is a bottom view of an electronic circuit device according to a second embodiment of the present invention. 1, 11...Substrate (insulating substrate), 2, 12...
External lead terminal (lead pin), 3...Circuit element (IC chip), 6, 13...Wire connection.
Claims (1)
電気的に接続された外部リード端子と、この外
部リード端子の少なくとも2本を電気的に接続
する上記基板上に直接、印刷、蒸着などにより
形成された結線と、この結線を選択的に切断す
るために上記基板上に集中して直接結合して設
けられた切断部とを有することを特徴とする電
子回路装置。 (2) 切断部が導電シールにより形成されているこ
とを特徴とする特許請求の範囲第1項記載の電
子回路装置。[Claims for Utility Model Registration] (1) A substrate holding a circuit element, an external lead terminal electrically connected to the circuit element, and the above-mentioned substrate electrically connecting at least two of the external lead terminals. An electronic device characterized by having a connection formed directly on the substrate by printing, vapor deposition, etc., and a cutting portion provided in a concentrated manner on the substrate and directly bonded to the substrate in order to selectively cut the connection. circuit device. (2) The electronic circuit device according to claim 1, wherein the cutting portion is formed of a conductive seal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980148228U JPS6242540Y2 (en) | 1980-10-16 | 1980-10-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980148228U JPS6242540Y2 (en) | 1980-10-16 | 1980-10-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5771350U JPS5771350U (en) | 1982-04-30 |
JPS6242540Y2 true JPS6242540Y2 (en) | 1987-10-31 |
Family
ID=29507691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1980148228U Expired JPS6242540Y2 (en) | 1980-10-16 | 1980-10-16 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6242540Y2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5540534B2 (en) * | 1973-08-30 | 1980-10-18 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4963657U (en) * | 1972-09-13 | 1974-06-04 | ||
JPS5540534U (en) * | 1978-09-05 | 1980-03-15 |
-
1980
- 1980-10-16 JP JP1980148228U patent/JPS6242540Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5540534B2 (en) * | 1973-08-30 | 1980-10-18 |
Also Published As
Publication number | Publication date |
---|---|
JPS5771350U (en) | 1982-04-30 |
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