JPS5924897A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument that generates musical tones using an electronic circuit, and more particularly to an electronic musical instrument that changes an envelope value asynchronously with a musical sound waveform. Electronic technology has advanced rapidly, and it has become possible to generate the sounds of musical instruments using electronic circuits. For example, an electronic piano generates a piano sound waveform using an electronic circuit, amplifies the waveform using an amplifier, and emits musical sound from a speaker. The same is true for electronic organs, in which an electronic circuit generates a musical tone waveform corresponding to the pressed key, and an amplifier amplifies this waveform to emit musical tone from a speaker. Electronic musical instruments that generate musical tones using electronic circuits such as those described above change the envelope, that is, the amplitude value of the sound, to make the musical tones closer to those generated by the musical instrument. For example, instead of outputting the maximum value of a musical tone at the same time as a key is pressed, the 1 cope value increases when a key is pressed, and when it reaches a certain value, the envelope value becomes constant at the above-mentioned certain value, After a certain period of time, the envelope value becomes small and finally reaches zero. The above-mentioned states are respectively called Atanku to'I゛, Digay[]C, and Lily Release. When a key is pressed, an attack state is entered and the envelope value increases, and when it reaches a specific value, a decay state is entered, and the envelope value remains at the above-mentioned specific value for a certain period of time. Next, after a certain period of time, it enters a release state, and the envelope value slowly decreases, and when it reaches zero, the degay state ends. On the other hand, there are two types of electronic musical instruments: one that generates musical tones through analog processing, and the other that generates musical tones through digital processing. The method of generating musical tones by Ana I: J processing is good when configuring one type of tone, but the circuit becomes complicated when configuring a plurality of musical tones. This is because musical instrument tones are obtained by providing filters with specific frequency characteristics.In order to output multiple types of tones, multiple filters are used, and in order to change the envelope independently of each other, multiple filters are used. This is because an analog multiplier must be provided. The method of generating musical tones through digital processing generates the waveform of musical tones as digital values, and then converts the digital values into

[)/A converter converts it into an analog value. A clock signal corresponding to the pressed key is generated, the clock signal is counted by a counter, and the contents of the waveform memory in which the waveform data is stored are read based on the value, thereby forming digital waveform data. The waveform data stored in the waveform memory is a differential value of the waveform, and the data read from the waveform memory is accumulated to form digital data of the waveform. In digital processing, the amplitude of the envelope is changed by differentiating the waveform read from the waveform memory (+A) by multiplying the waveform data by the envelope value and summarizing the result. There are two types of generation: one is generated by analog processing, and the other is generated by digital processing. However, with advances in LSI technology, it has become possible to easily perform digital processing, and now most cases are generated by digital processing. be. Electronic musical instruments that generate musical tones through digital processing.
C is also processed to have the attack, digital, and release states described above. In the case of digital processing, instead of multiplying the accumulated result by an envelope value, the envelope value is multiplied by the waveform data before accumulation, that is, the differential data of the waveform, and the envelope value is changed by -1.
The timing at which data is generated is limited to the digital data of a specific waveform. Generally, the timing when changing the envelope value and multiplying the waveform data, which is the differential data of the waveform, is when the cumulative value is O.
It was time to do so. Figure 1 (al) to (6) are timing charts showing each timing of the electronic musical instrument, in which the multiplication timing described above is when the accumulated value becomes 0. The waveform timing clock EXC enters the address counter that specifies the address of the memory storing the basic waveform.The waveform shown in Figure 1 will be explained below assuming that it is a pulse-like waveform stored in the memory. That is, one waveform is made up of four clocks, and the timing clock EX
When the timing clock is EXC2, the basic waveform data is -1-1, and when the timing clock is EXC2, it is 0. timing clock EXC
When the signal is 3, -1 is output from the memory, and when the evening/timing clock EXC4 is, O is output from the memory. Fig. 1 fb) 4J synchronization signal 5YNG is not shown. The synchronization signal 5YNC is a system clock for the system to operate in synchronization with the signal, and the attack signal ATT (FIG. 1 (C1), enrobe clock EVcK8 (i:
f Kawaguchi + il +), envelope value EV (Fig. 1 te
l), en・\rope status EVST (Fig. 1 (
f)) l, : l knee 1'bei changes in synchronization with this signal. The attack signal ATT is a signal indicating the start of an attack,
Output when a key is pressed. The envelope 1:1-p status EVS'[' becomes attack AT due to the Zuna straw signal. The envelope clock IEVCK is a signal that provides the timing at which the envelope changes, and the envelope value E■ changes according to this signal. At the start of the attack, the envelope value EV becomes 0, and the envelope value EV becomes 3 at the same time as the start clock. The musical sound waveform MW rises from O to 3 according to the timing clock EXC1. Timing Clock E
In X C2, timing clock EXC3, timing clock EXC4, its envelope value EV
has not changed, so the tone waveform MW changes from 3 to 0 again. At the next synchronization signal 5YNC, the envelope value EV becomes 6, and the musical tone waveform MW becomes 6. Furthermore, with the next synchronization signal 5YNC, the encoder status EVST becomes DIDC, and the envelope value EV becomes 7. 1st
In the figure, the time of decay I)C is short, and release RL occurs at the next clock. In release RL, the envelope value EV is 6, 5, 4, 3, 2 with sequential synchronization signal 5YNC.
．． 1, and finally the release RL ends, that is, the amplitude becomes O (in al to fgl, the envelope value EV
were all changed when the waveform value reached 0, that is, when the cumulative value reached 0. As a result, the cumulative value always ended up being 0. In this method, the envelope value EV is changed in synchronization with one period of the musical tone, that is, the 1gI type, so the timing at which the envelope value EV is changed only exists once every -111 period. Therefore, it is not possible to gradually change the envelope value EV from, for example, 0 to 7 in one cycle, and only large envelope changes such as 0, then 4, and then 7 can be applied. 1st
In the example shown in the figure, it changes to 3 and 6 in two cycles. This is equivalent to an increase in the range of change in the envelope and a decrease in the apparent number of bits of the envelope, which may lead to problems such as the generation of clock noise, resulting in a musical tone with difficult intervals. On the other hand, as a way to solve this problem: [Nherop value I
A method has been proposed in which EV is changed without synchronizing with the synchronization signal 5YNC. Fig. 1 (11) - (kl is the timing check of the method in which 1 column is changed to the encoder asynchronously with the synchronizing signal 5YNC,
-1, not shown. Note that the timing clock EXC, synchronizing signal 5YNC, and actuating signal A'T''T are the same as in the previous case, and refer to FIG. 1 (al to (C)). The envelope value EV' changes asynchronously with 5YNC, and the envelope value EV' changes as the envelope value EVCK' changes. l", and 1 unit to 1 unit EV
CK' causes Koninhe I:I-B (direct EV' to become 1. At this time, since the timing clock 1jXc1 is -+-1, the musical sound waveform MW' changes from 0 to 1. Next, the synchronization signal sequence 5YNC and Irrespective of the envelope black/tsuk EVC
K' is output, and the envelope value EV' becomes 2. During this time, there is a timing clock 1:J = EXC2, but since the basic waveform data is 0 at this time, the musical sound waveform MW' at this time does not change. because,
This is because the basic waveform data in this method is a differential value, and the musical sound waveform MW' is obtained by multiplying the basic waveform data by the envelope diameter and adding the result. At the same time as the next envelope clock EVCK', the envelope value EV' becomes 3. However, since the timing clock EXC has not yet been output at this time, there is no change in the tone waveform MW'. This change is made in one timing EXC3. This is because the basic waveform data is -1 at timing clock EXC3. That is, the basic waveform data and the envelope value EV' are multiplied and accumulated by the clock of the evening timing clock EXC3. As a result, the tone waveform MW' becomes -2. Similarly, the envelope value EV is sequentially determined by the envelope clock EVCK'.
' changes from 4.5°6.7, and the envelope status Ev s "' also becomes Decay DC. As a result, the tone waveform MW' changes from -2 to +3.-4.+3...
and 'A-'. Furthermore, the envelope status EVS'
l'' changes from Decay DC to Release RL, and En's 1.1-puhani EV' also decreases to 6, 5.4, etc., and becomes 0 at Noiso Yufuyu 1 White. J en 11-bus status E
When V S i'' is release RL, the interval between the Koninherob crosses EVCK' is long, and as a result, the musical sound waveform MW' gradually becomes smaller.The above operations are repeated one after another, but eventually the envelope (When the direct EV' becomes 01 and the release RL force becomes 0, the musical sound waveform MW' may not become O in this method.The musical sound waveform MW' shown in FIG. As mentioned above, the final accumulator converts the musical sound waveform to f without the absolute value.
In the W method, if the envelope (+ff) is changed at a point other than where the accumulated value is O, a DC component will remain, and the operation in which a key is pressed and a musical tone is generated without these operations is When repeated sequentially, the DC component becomes a dog,
For example, the dynamic range of a digital-to-analog converter may be reduced or even exceeded. For this reason, the asynchronous method has various problems. The present invention eliminates the residual DC component that occurs in an asynchronous system, and its purpose is to provide an electronic musical instrument characterized by making small amplitude changes asynchronously and generating multiple musical tones simultaneously. be. The present invention is characterized by a first clock generation means for generating a scale clock corresponding to the pressed key, a memory storing differential data of the fundamental waveform, and an input scale clock corresponding to the pressed key. The second one that generates a heroic cross
a multiplication circuit 1tδ for multiplying data obtained by reading the contents of the memory in relation to the first clock generation means by an envelope value related to the second clock generation means; and a DC correction circuit. and an adder circuit,
Shift Me: E: Consists of an accumulator circuit and a digicrew analog converter, and inputs the output of the DC correction circuit to the shift memory and reads the contents of the shift memory at the same time as shifting. adding the value and the output of the multiplication circuit in the adder, and storing the result again in the shift memory;
An electronic musical instrument characterized in that a plurality of musical tones are simultaneously output by accumulating the shift outputs of the shift memory and converting the accumulated results into analog values by a digital-to-analog converter. be. Hereinafter, the present invention will be explained in detail using the drawings. In the conventional method described above, after the point of change, the multiplication with the new input value and the accumulation are performed correctly. However, the values that have already been output but have already been accumulated use old envelope values, and the aforementioned DC component is generated by accumulating the multiplication results of those values and the new envelope value. There was a problem that occurred. The principle of the present invention is to add a correction value to the old accumulated value and correct it so that it becomes the accumulated value based on the new envelope value. The aforementioned DC component value Er is expressed as a function of the waveform differential value Δ, the envelope value n of the change 1 &, and the envelope value 0 before the change, −Er−ΣΔX (n−0) . (1) becomes. Here, assuming that the envelope value changes by only ±1 with respect to the enrobe clock EV CK, it becomes -E r -±ΣΔ ・・・・・・・・・(2); The principle of the present invention is that the change in envelope value with respect to envelope value EVCK is ±1,
cII, ΣΔ is calculated in advance, and when the envelope value changes, the current ΣΔ is added as a correction value of 7 for correction. FIGS. 2 and 3 show waveform diagrams of a conventional system and a waveform diagram of the present invention, respectively. Fig. 2(b), Fig. 3 (bl is waveform data,
Figure (a), Figure 3 (al is the accumulated value of the value Zunawajien-, the musical sound waveform when the rope value is 1), and Figure 3 (C1 is the digital value at that time) This value is the aforementioned ΣΔ, and is shown in Figures 2(c) and 3(d).
If the envelope value changes as shown in ), the musical sound waveform at that time will become as shown in Fig. 2(d) and Fig. 3+e). As shown in Figure 2+d+, in the conventional method, a DC component remains in the final value, but in the present invention, as shown in Figure 3 (el), the DC component is corrected. , This is because when the I cope value changes asynchronously, the ΣΔ at that time is added and corrected.
Step STP shown in FIG. 3(e) is a step resulting from this correction. ffs Figure 4 shows a circuit configuration diagram of an embodiment of the present invention. Note that the same symbols as the conventional symbols described above are used for signals and the like. Scale clock generation circuit 1. status counter 2,
Envelope counter 3. The Enherodec 1:1 output circuit 4 is connected to the LJ sensor CPU. scale l
"EXC signal of dock generation circuit 1 [J gate circuit G1
and the first input terminal of the AND circuit AN I) and the +1 input terminal of the 71-counter 5. The 5YNC output of the address counter is 1] C sleeve correction Raku 6. Enherobug 1'J ivy inhibition circuit 7゜attack synchronization section 8 5Y
Input to the NC input terminal. Note that the attack synchronization section 8. The connection of 5YNC that is input to the encoder block 1 check inhibition circuit 7 is omitted in the figure. The address output 0114 of the address counter 5 is connected to the address glass of the differential value waveform memory 9. Its output is the multiplication circuit 10. The DC correction circuit 6 is manually powered. The attack synchronization section 8 further includes an attack-on signal ATTO.
N is input, and its output is input to status counter 2. AT output glass of status counter 2 is OR circuit O
is connected to the first input terminal of R. R1-output ☆11,
The first child is the second input terminal oC? of the aforementioned OR circuit OR. i
li positive circuit 6° connected to envelope counter 3. The output of the OR circuit OR is input to the second manual glass of the AND circuit AND, and its output is input to the DCC positive circuit 6. DC output of status counter 2 &Ii:l terminal is bold 61M1 terminal of bold circuit 11, stop signal S T
61M1 child is envelope clock inhibition circuit 7. The signals are respectively input to the correction prohibition circuit 12. The output of envelope counter 3 is bold times 1t'& 11. The square calculation circuit 10 is connected to the addition input terminal of the addition circuit 13 via the gate circuit C1. Further, the carry output of the envelope counter 3 is input to the status counter 2. The envelope clock l:I, , , of the envelope clock generation circuit 4 is input to the Koninhero clock 1 cock inhibition circuit 7, and its output is input to the envelope counter 3 and the correction inhibition circuit 12. The encoder output of the correction inhibition circuit 12 is input to the gate input of the gate circuit G2. DC correction circuit 6
The output is input to the latch 15 via the gate circuit G2. fJ and 1 of the latch 15 are connected to the shift I memory 16. The auxiliary circuit 1iI813 is connected to the shift memory 16 'I6', and the shift output of the shift memory 16 is inputted to the accumulation circuit I4. In addition, shift memory 1G has a musical scale [
An address signal from the multiple occurrence circuit 1 is input. Although not shown in FIG. 4, the output of the accumulator circuit 14 is connected to a digital-to-analog 1-cog converter D/A. The operation of the embodiment of the present invention shown in FIG. 4 will be explained below using the timing chart shown in FIG. The signal of the pressed key is detected by the processor CPU T: and data corresponding to the pressed key is input to the scale clock generation circuit I/&1. The scale clock generation circuit 1 generates a clock corresponding to the data, that is, a timing clock EXC (FIG. 8(b)), and the address: ζ
The data in the non-counter 5 is incremented. The data in the counter 5 is sequentially incremented in response to the timing clock EXC and stored in the differential value waveform memory 9.
access address A of . It also generates a synchronizing signal 5YNC (FIG. 8(C)). The synchronization signal 5YNC is a carry of the address counter 5, and is a signal that does not indicate that the contents of the address counter 5 newly start from 0. The differential value waveform memory 9 outputs the memory data specified by the address counter 5 mentioned above. The data (I+1 in FIG. 8) stored in the differential value waveform memory 9 is the differential value of the musical tone, and is input to the DCC correction circuit 6 East 10. f)), and in synchronization with the next synchronization signal 5YNC, the attack signal A T T
(FIG. 8(g)) is output to the status counter 2. The status counter 2 counts the carry output of the envelope 1 cove count 3, that is, the status change signal (Fig.
It outputs each status signal of C and release RL. Figure 8+11 AT those statuses. 1) Indicated by C and RL, respectively. Note that EP is a status that does not belong to the above-mentioned statuses, and indicates that the status counter 2 is empty (blank). The status counter 2 also outputs a stop signal -3-sT. This signal is inputted to the envelope clock I'k weighting circuit 7, which outputs the envelope clock 1:11, .
Figure +11). Envelope clock starting times 11 & 4
is the circuit that generates the envelope clock E V CK (see Figure 8 (11)).
wo: c 7 he 1: I -f/)rono/7 %j Signal to the stop circuit 7. To JC7 LJ - Fuku II Tsuku V main b'& 7 is the stop signal M' ST generated by status counter 2.
K; f: Decide whether to stop M or not. FIG. 8U) shows the signal EVCKX, which is input to the counter 3. The envelope counter 3 is a circuit that forms a gondola waveform according to instructions from the processor cPU, and at the same time as the attack AT.
Count the CKX pulses. Also, during decay DC, the pulse of EVCKX is turned on. Release RL of status counter 2 is envelope counter 3
(11) When the input signal is input to 10/-6M1 and the envelope counter 3 is released RL, a decrement operation is performed from the maximum envelope value in the opposite manner to the above. The output of envelope counter 3 is bold times 12δ11
When it is attack AT or release RL, it passes through bold circuit 11 and is input to multiplier circuit 1o. In the case of decay DC, the maximum value of the envelope counter 3 and the final value of the attack AT are bolded by the bold circuit 11 and input to the multiplication uIIδ10. This number 1<- field circuit 11 is a circuit h111 for bolding the maximum value of the envelope at the time of decay DC, and since the envelope counter 3 counts the decay I) C115b, this value is sent to the multiplication circuit 10 +, 'This is a circuit that prevents manual effort. The multiplication circuit 10 is a circuit that multiplies the data of the differential value waveform memory 9 and the data of the halt circuit 1, and
- Outputs the differential value of the musical sound waveform corresponding to the tap value. The value is input to the addition circuit 11'813 via the J gate circuit G1, and the gate of the gate circuit G1 is turned on by the timing clock EXC, and the value is input to the addition circuit 13 at the timing of the timing clock EXC. - On the other hand, the OR circuit OR calculates the logical OR of each state of attack AT and release RL, and when either attack AT or release RL occurs, the AND circuit AND's gate 1 -
Turn on the timing check 1 dock E to the DCC positive circuit.
Input the XC signal (Fig. 8(e)). This is because there is no need for correction when using Decay DC, and only when using Attack A'F and Release RI-.
111 positive value is found. Further, a synchronizing signal 5YNC is input to the DC correction circuit 6. This is because when the address counter becomes zero, the contents of the DC correction circuit 6 are also cleared at the same time. That is, the DC correction circuit 6 accumulates the data obtained from the differential value waveform memory 9 only at the time of attack AT and release RL, and inputs the value to the addition circuit 13 via the gate circuit G2. This is done by the timing clock EXC, and is constantly cleared by the synchronization signal SYNC every one cycle of the musical tone. FIG. 8 (dl does not indicate the correction value of the DC correction circuit 6. In the present invention, correction must not be performed at the time when the status changes. The correction prohibition circuit 12 and the gate circuit prohibit this correction. G2.When the stop signal ST outputted from the status counter 2 by the correction prohibition circuit 12 is at H level, EVCK
is not output, but is output when the level is I5. The output of the correction prohibition circuit 12 is input to the gate circuit G2, and
C? Controls whether or not the correction value of the ili positive circuit 6 is input to the latch I5. In other words, the gate is turned on only when l cock is output from the correction prohibition circuit 12, and the DC
The correction value of the correction circuit 6 is inputted to the latch 15 and written as jQ. The adder circuit 13 has a function of adding successive data from the shift memory 16 and data manually input from the multiplier circuit 10 via the gate circuit G1, and the result is stored in the shift memory 16 again. Reading of the data from the shift memory 1G is specified by an address output from the scale clock generation circuit 1. That is, the shift memory 16 shifts sequentially stored data to the accumulation circuit 141 according to the system clock φS, and further transfers the contents of the memory designated by the scale clock generation circuit l to the addition circuit 13.
2'lS Embodiment 4J of the present invention shown in Fig. 4 has a function of simultaneously generating multiple tones, and has a scale clock generation circuit. 1. Status counter 2. Envelope counter 3
．． Enheropook 1 cock generation circuit 4゜address counter 5', DC correction circuit 6. Enherobe clock inhibition circuit7. Each of the tank synchronizers 8 is equipped with a shift register for generating a plurality of tones. These shift 1 to registers shift data by system clock φS,
Each operation described above using FIG. 8 is performed every time there is a shift. In other words, the shift register constitutes a closed loop so that each function can be performed, and the data is shifted in a loop by the system clock φS, and the operation described above is performed while generating the corresponding musical tone. Ru. The aforementioned? Operations corresponding to the 51 musical tones are performed sequentially and stored in the Schiff I memory. Data related to DC correction is input to the shift input of the shift memory 16 via the latch 15, and is sequentially shifted to the output side. Further, the change value of the musical tone is input to the adder circuit 13 via the gate circuit G1, but the augend at this time is the content of the shift memory 16 specified by the scale clock generation circuit 1, and the result is the content of the shift memory 16. Enter the same number in 16. The shift memory is provided in order to adjust the frequency accuracy of musical tones to the level of the system clock φS. The shift output of the shift memory 16 enters an accumulation circuit 14 and is accumulated. Since the contents of the shift memory only store DC correction values and musical tone change values, they are divided to generate a digital value of a composite wave of a plurality of musical tones. Although not shown in the embodiment of the present invention in FIG. 4, the output data is input to a digital-to-analog converter D/A, becomes an analog I:l signal, and is output to a speaker via an amplifier. is output as musical sound. FIG. 8(b) shows the output waveform of the digital-alley-log conversion path. This is a chart 1 diagram for generating a musical tone shown in FIG. 8, which is based on the system clock φ
S is repeated sequentially. For example, if each shift register has 8 steps, the steps are sequentially repeated in units of 8 steps. g(s) Figure 5 shows the circuit diagram of the actuator synchronization section 8. The actuator and quon signal A Ti"ON enters the OR circuit 01,
The output is input to each input of AND circuits ANI and AN2. The output of AND circuit 1/&A N 1 is in register R1
The signal is input to OR circuit 01 via. On the other hand, synchronization signal 5Y
NC is input to an AND circuit AN2, and its output is output to the status counter 2 as an attack signal ATT, and is also input to the AND circuit ΔN1 via an inverter Il. OR circuit O1, Nl to AND circuit, and register R1 form a loop, and actuate on signal A.
The r'I" ON signal is stored in this loop. That is, when the ac/7 quon signal 8"I" T ON is input, the input voltage of the shift register becomes H level,
N2 is turned on to the AND gate circuit every time the shift register R1 goes around. As a result, the synchronizing signal 5YNC of the method is outputted as an attack signal AT' through the AND circuit AN2, and is also outputted as the tent signal A'T' through the inverter 11.
Input to l'l AN 2 and set the shift register's large level to I77. FIG. 6 shows each circuit diagram of the DCC positive/positive circuit 6-gate circuit G2. The output of the AND circuit AND is the AND circuit Δ
It is commonly input to the first gates of N3 to AN6. M) This, the differential value from the differential value waveform memory 9 is stored in the AND circuit AN3~
input to the second gate I of AN6. AND circuit AN3
The output of ~AN6 is added to the 6-bit full adder FA's addition manual BO-13 via the exclusive OR EORI~EOR4.
Enter 3. On the other hand, the release old 7 of the status counter 2 and the minus signal number IJ of the differential value waveform memory 9
Input the signal (Yoki Chusu - human power Ci and ()1 Alternative logic OR EORI
~ EOR4 and full adder F” A’s additional human power B4.B5
Enter. The synchronizing signal 5YNC is input to the reset terminal inputs of registers R2 to R7. The addition signal SO to addition signal S5 of the full adder FA is input to the registers R2 to R7, and the signals are applied to the AND circuits AN7 to ΔN12 and the augend inputs AO to Δ5 of the full adder FA. Further, the output of the correction inhibition circuit 12 is commonly connected to the other gates of the AND circuits ANT to AN12, and the output is
Input in notch 15. AND circuits AN7 to AN12 are the gate circuits G2 shown in FIG. The signal input from the differential value waveform memory 9 is input to the AND circuit Δ by the timing clock EXC input via the AND circuit AND.
The gates of N3 to AN6 are turned on, and the exclusive logic OR E
It is added to the value stored in the output node of the shift register I≧2 to R7 in the full adder FA via ORI to EOR4. The results are output from the addition signals SO to S5 and stored again in the shift registers R2 to R7. 1 no 1. The output of the alternative logic OR EOR5 is a signal specifying addition or subtraction, and when the output is at H level, it is a subtraction operation.[When it is 7L/bell, it is an addition operation. Full adder FA is added, but IJI connected to addition input BO~B3: IIl+ logical OR EOR1~
Conditions by EOR4]1. There are cases where a two's complement number is created. In this case, the number is subtracted by 1. +11 at the time of attack AT and release RL; since the positive value is reversed, the processing is determined by the exclusive OR of release RL and differential value waveform memory 9 in exclusive logic OR BOR 5. That is, in the release RL state, the output of the exclusive OR EOR5 becomes an addition signal when the data in the differential value waveform memory 9 is negative, and becomes a subtraction signal when it is positive. Also, when it is not in the release RL state, the data in the differential value waveform memory 9) (when it is negative, it becomes a subtraction signal; when it is positive, it becomes an addition signal. The shift registers R2 to R7, which store the addition results of the full adder FA, are envelope values. has the musical waveform values of multiple musical tones when is l, but the sign is the release RL as described above.
When , 4J is reversed. Schiff!・The same IUI signal 5YNC input to the reset throat terminals of registers R2 to R7 changes the input mold throats of shift registers R2 to R7 in units of one period of musical tone.
This means that the data stored in the shift registers R2 to R7 has a negative or negative direction depending on the status, and they are synchronized. input to display. In other words, synchronous signal '1
To completely synchronize with 4SYNC (clear the corresponding bits of the shift registers R2 to R7). ．／
7. ? A circuit diagram of the di-prohibition circuit 12 is shown. Enherotsuburi I-1 Tsuku occurrence 1ill! 1 path 4's Kornbe I Korburi tsuku EVC1 (and circuit A
input to the first input of N13. On the other hand, the synchronizing signal 5YNC is input to the jitter register R9 via the OR circuit 02, and the stop signal ST is input to the inverter +
3. AND circuit 1/1) ANS, input to shift register R9 via OR circuit 02. The output of the shift I register R9 is input to the AND circuit AN13.
Input to circuit ANS. The output of the AND circuit AN13, ie, EVCKX, is input to the AND circuit AN14 of the en-rope counter 3 and the correction inhibition circuit 12. The AND circuit AN14 also receives a stop signal ST and the inverter I2.
]3, and its output is input to the gate circuit G2 via the shift register R8. When the stop signal ST is input, the inverter 13. Anne 1 circuit ANS
, the input voltage of the shift register R9 via the OR circuit 02 becomes I level. Then, the signals are sequentially shifted and output to the AND circuit AN13. When the output of the shift 1 register R9 is at L level, the envelope relock EV CK input to the amplifier circuit ΔN13 is no longer output. When synchronization signal 5YNC is input next to stop signal ST,
When the input voltage of the shift register R9 becomes I (level) and H is output to the output bit of the left shift register R9 by the system clock φS, N13 is turned on to the AND circuit and the enrove cross IE V C
K is output. The Zuna straw signal is EVCKX, which is input to the enherobe counter 3 and also to the AN1 circuit AN14. That is, when the stop signal ST inputs the bit of the shift register corresponding to one of the plural musical tones, the bit of the shift register corresponding to one of the plural musical tones is input. Write down a flag that prohibits manual input (set to 1).
1-acl'' (EVCK) is outputted via the AND circuit AN13. To En at this time (Kopuku l: l
It is the correction prohibition circuit 12 that prohibits the EV CK X from being inputted to the shift register R8 when the AND circuit AN14 is turned off by an invert signal of the stop signal S'F. Fig. 8 (m+ is the correction enable input to the gate circuit G2 (j <1;). Fig. 8 (m+ is marked with an The present invention has been described above in detail using one embodiment. According to the present invention, the envelope can be changed many times within one period of the musical sound waveform, and the envelope can be changed rapidly. Even if the shift register 110 changes, no DC component remains, and it is possible to create an electronic musical instrument that simultaneously generates multiple tones closer to the musical tones of the musical instrument.In the embodiment of the present invention, the shift register 110
~R9 only needs to have the number of shift stages that can generate 1M musical tones at the same time, for example, up to 8 musical tones at the same time? In the case of L, an 8-step shift register is sufficient. Furthermore, in the embodiment of the present invention, the change in envelope value is ±1
I explained it as, but this. It is also possible to increase the value to 2.3 by multiplying the output of the DC correction circuit by a change value.

[Brief explanation of the drawing]

Figure 1 shows the quimming chart I of a conventional electronic musical instrument, where (.1) is the timing clock, tbl is the synchronization signal, (H]) is the attack signal, (dl, (hl is the envelope clock 1), + 7ri, tea, (en is to en
The core value, if), fJ) indicates the envelope status, fgl, (kl indicates the musical sound waveform, respectively.
The figure is a basic waveform diagram of a conventional electronic musical instrument, Figure 3 is a basic waveform diagram of an electronic musical instrument of the present invention, Figure 4 is a circuit configuration diagram of an embodiment of the present invention, and Figures 5 to 7 are its circuit diagrams. , FIG. 8 is a timing diagram of the electronic musical instrument of the present invention-1. (a) is the waveform differential value, fbl is the timing clock, (C) is the synchronization signal, (dl is the correction value, (el is the data 1 ~ signal train, (f
l is the actuon signal, (g+ is the attack signal, (11
) is the control signal for outputting the encoder clock, (+), (Jl is the encoder), (1)
() indicates a status change signal, +11 indicates an envelope status, tml indicates a correction enable signal, and (1)) indicates a musical sound waveform. 1... Scale generation circuit, 2... Status counter, 3... Cone clock force 1 sink, 4... Enherobe clock destination circuit, 5...
...Address counter, 6...DC correction [IG,
7...Envelope clock inhibition circuit, 8...
Attack synchronization section, 9... Differential value waveform memory, 10
...Multiplication circuit, 11...Hold circuit, 12
...correction prohibition circuit, 13...addition circuit, 14.
... Accumulation circuit, CI) U... Processor, Gl,
G2...Kate circuit, OR, 01...OR circuit,
AND. ANI-ANI4. ANS...An 1° circuit, R1-
R9...Shift register, ■1~I3...Impark, EORI~EOR5...Exclusive logical OR,
FA... Full adder, SRF F... Sen 1
-Lise Sotfrisopf 111, Nobu. Patent applicant: Yoshiyuki Osuga, patent attorney for Casio d1° Computer Co., Ltd. Figure 2, Figure 13

Claims (2)

[Claims] (1)' A first pitch-knock generating means for generating a scale clock corresponding to the pressed key, a memory storing differential data of the fundamental waveform, and an engine l-knock generating means corresponding to the pressed key. a second clock generation means for generating clock pulses, data read from the memory contents related to the first clock generation means, and an engine 21- related to the second clock generation means; The output of the DC correction circuit is input to the shift memory and shifted. At the same time, the contents of the shift memory are read, the value obtained by this system is added to the output of the multiplication circuit by the adder, the result is stored again in the shift memory, the shift output of the shift memory is accumulated, and the output of the shift memory is accumulated. An electronic musical instrument characterized by outputting multiple musical tones simultaneously by converting the results into analog values using a digital-to-analog converter. (2) Above 1. Second clock generation means, DC 211
Each positive circuit has a plurality of registers and stores data corresponding to a plurality of musical tones. An electronic musical instrument as set forth in item 1 of the scope of patent application No. 11, characterized in that a plurality of musical tones can be output simultaneously by a.