JPS5924898A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument that generates musical tones by changing an envelope value asynchronously with a fundamental waveform.

Electronic technology has advanced rapidly, and it has become possible to generate the sounds of musical instruments using electronic circuits. For example, an electronic piano generates a piano sound waveform using an electronic circuit, amplifies the waveform using an amplifier, and emits musical sound from a speaker.

The same is true for electronic organs, in which an electronic circuit generates a musical tone waveform corresponding to the pressed key, and an amplifier amplifies this waveform to emit musical tone from a speaker.

On the electronic musical instrument side, which generates musical tones using the electronic circuit described above, by changing the envelope, that is, the amplitude value of the sound, the musical tones are made closer to the musical tones generated by the musical instrument. For example, instead of outputting the maximum value of a musical tone at the same time as a key is pressed, the envelope value increases when a key is pressed, and when it reaches a certain value, the envelope value remains constant at the above-mentioned certain value. After a certain period of time, the envelope value becomes small and finally becomes zero.

The states like the previous iJ are respectively called attack AT, degay DC, and release RI. When a key is pressed, it goes into attack state and the envelope value increases, and when it reaches a certain value, it goes into decay state and the envelope value stays at the above-mentioned specific value for a certain period of time. Next, after a certain period of time, it enters the release state, and the en-1''-bu value slowly decreases, and when it reaches zero, the dig/child state ends.

On the other hand, there are two types of electronic musical instruments: one is to generate musical tones by alley-log processing, and the other is to generate musical tones by digital processing.

The method of generating musical tones by analog cog processing is good when configuring one type of tone, but the circuit becomes complicated when configuring a plurality of musical tones. This is because musical instrument tones are obtained by providing filters with specific frequency characteristics.In order to output multiple types of tones, multiple filters are used, and in order to change the envelope independently of each other, multiple filters are used. This is because an analog multiplier must be provided.

In the method of generating musical tones through digital processing, the waveform of musical tones is generated as digital values, and the digital values are converted into analog values using a D/A converter. A clock signal corresponding to the pressed key is generated, the clock signal is counted by a counter, and the contents of the waveform memory in which the waveform data is stored are read based on the value, thereby forming digital waveform data. The waveform data stored in the waveform memory is a differential value of the waveform, and the data read from the waveform memory is accumulated to form digital data of the waveform.

In digital processing, envelope-like amplitude changes are performed by multiplying the waveform data, which is the differential value of the waveform read from the waveform memory, by the envelope value and accumulating the results.

As mentioned above, there are two types of electronic musical instruments: one that uses analog cog processing and the other that uses digital processing. However, with the advancement of LSI technology, it has become possible to perform digital processing, and now Most of them are processed digitally.

Even in electronic musical instruments that generate musical tones through digital processing, processing having the attack, digital, and release states described above is performed. In the case of digital processing, the cumulative result is: instead of multiplying the Lnherop value by 11 days,
The envelope value is multiplied by a number on the differential data of the waveform as well as the waveform data before being accumulated, and the timing at which the envelope value is changed is limited to the digital data value of a specific waveform.

Generally, the timing for multiplying waveform data, which is differential data of a waveform, by changing the 1-1-p value is when the accumulated value becomes O.

FIGS. 1(8) to 1(g) are timing charts showing each timing of the electronic musical instrument, in which the above-mentioned multiplication timing is when the cumulative value becomes 0.

FIG. 1 f8+ does not show the waveform timing clock EXC. The waveform timing clock EXC enters an address counter that specifies the address of the memory storing the basic waveform. The following explanation will be given assuming that the waveform shown in FIG. 1 is a pulse-like waveform stored in the memory. In other words, four clocks form one waveform, and the timing clock EXC
When I, the basic waveform data is +1. timing clock E
0 for XC2. -1 is output from the memory when the timing clock is EXC3, and O is output when the timing clock is EXC4.

1st lk! J (bl indicates the synchronization signal 5YNC. The synchronization signal S Y N C is the 1'/STE J2 clock for the system to operate in synchronization with that signal, and the attack signal ATT (i:fs1 figure (e ) ) , x y
Herop""So') EVCK (Figure 1 (++l
), envelope value EV (F81 in FIG. 1), and envelope status EVST (FIG. 1(f)) change in synchronization with all signals.

The attack signal ATT is a signal indicating the start of an attack,
Output when a key is pressed. In other words, this signal causes the envelope status EVSi' to become attack 8T. The encoder EV CK is a signal that gives the timing at which the envelope changes, and the envelope value EV changes according to this signal. At the start of the attack, the engine I:I-p value EV is 0, and at the same time as the start clock, the engine I:I-p value EV is 3.
becomes. The musical sound waveform MW rises from -ζO to 3 by the timing clock EXC1. Since the envelope value EV has not changed in the timing clock EXC2, the timing clock EXC3, and the timing clock EXC4, the musical sound waveform M'W changes from 3 to 0. At the next synchronization signal 5YNC, the envelope value EV becomes 6, and the musical tone waveform MW becomes 6. Furthermore, with the next synchronization signal 5YNC, the envelope status EVST becomes degay DC, and the envelop 1:J-p value EV becomes 7. 1st
In the figure, the decay DC time is short (, and the next clock becomes the release RL. In the release RL, the synchronization signal 5YNC is applied sequentially).
3.2.1, and finally the release RIJ% is completed, that is, the amplitude becomes 0.
iff EV was changed when the waveform value and the cumulative value reached O. As a result, the cumulative value always ended up being O. In this method, the envelope value EV is changed in synchronization with one period of the musical tone, that is, one waveform, so that the timing of changing the envelope value EV to i exists only once in one period. Therefore, it is not possible to gradually change the envelope value EV from, for example, 0 to 7 in one cycle, and only large envelope changes such as 0, then 4, and then 7 can be applied. In the example shown in FIG. 1, the value changes to 3 and 6 in two cycles. This is equivalent to an increase in the range of variation in the envelope and a decrease in the apparent number of bits in the envelope, which may lead to problems such as the generation of clock noise, resulting in musical sounds that are difficult to hear.

On the other hand, as a way to solve this problem, the envelope value EV
A method has been proposed in which the value is changed by -1 without synchronizing with the synchronization signal 5YNC.

t (Figure 1 (11) to (kl) are timing keys that change the envelope asynchronously with the synchronization signal 5YNC.
-1-- indicates. In addition, timing black/tsuku EXC
, old 1st period signal 5YNC, AC signal A 'f' T
4. This is a difference between the above case and the case shown in Fig. 1 (a+~(C1
(see ).

This method is asynchronous to the same 11JI signal 5YNC (
The cope clock EVCK' and the envelope value EV' change, for example, the envelope status EVS changes at the same time as the acknowledge signal AT'F.
T 'forcefully actuates A'r, and by enveloping the envelope EVCK'
Is 1?

At this time, the musical tone waveform MW' changes from 0 to 1 because the timing EXCI is 1. Next, synchronization signal 5
Enhe 1 regardless of YNC” - Pukuro Tsuku EVCK
' is output, and the envelope value EV' becomes 2. During this time, the timing clock EXC2 exists, but since the basic waveform data is 0 at this time, the tone waveform MW' at this time does not change. This is because the basic waveform data of this method is a differential value, and the tone waveform MW' is obtained each time the basic waveform data is multiplied by an envelope value and added. At the same time as the next envelope clock EVCK', the envelope value EV' becomes 3. However, since the timing clock EXC has not yet been output at this time, there is no change in the musical tone waveform MW'. This change is made by timing clock EXc3. This is because the basic waveform data is 1 at the time of the evening C ming clock EXC3. In other words, h(
This waveform data and the envelope value E■' are multiplied and accumulated. As a result, the tone waveform MW' becomes -2. Similarly, the envelope value EV' changes sequentially to 4, 5, 6°7 by the encoder clock EVCK', and the envelope status EVST' also becomes degay DC. As a result, the tone waveform MW' changes from -2 to +3. -4. +3
...changes. Furthermore envelope status EVS
T' changes from degay DC to release RL, and the enhe1 cope value EV' also decreases to 6, 5.4, etc., and finally becomes 0. When Enherobesu r-1's EVST' is release RL, Enherobe 1 Corps Kurotsuku fE V
The interval between CK' is long, and as a result, the tone waveform M
W' becomes smaller slowly. The above operations are repeated sequentially, but when the envelope value EV' finally becomes 0 and the release RL becomes 0, in this method, the musical sound waveform M
There are cases where W' does not become 0. The tone waveform MW' shown in FIG. 1 fkl is -1.

As mentioned above, in the method of obtaining a musical sound waveform by calculating the absolute value in the final accumulator, if the envelope value is changed at a point other than where the accumulated value becomes 0, a DC component will remain, and these If the operation, that is, the operation in which a key is pressed and a musical tone is emitted, is repeated in sequence, the DC component will become large.
In some cases, the value may even be exceeded. For this reason, the asynchronous method has various problems.

The present invention has solved the above problems, and its purpose is to make it possible to create small amplitude changes asynchronously, for example, even at the time of attack.

At least one of the following statuses: Decay, Release, etc.
An object of the present invention is to provide an electronic musical instrument that generates musical sound waveforms without individual statuses.

The present invention is characterized by a first clock generating means that generates a scale clock corresponding to the pressed key, a memory storing differential data of the basic waveform, and a scale clock corresponding to the pressed key. NS that generates Enhero Furirosoku
a multiplication circuit that multiplies data obtained by reading the contents of the memory in relation to the first clock generation means by an envelope value related to the second clock generation means; and a DC correction circuit. and an addition circuit that adds the output of the multiplication circuit and the output of the DC correction circuit, and an accumulation means that accumulates the output of the addition circuit, and performs digital-to-analog conversion from the output of the accumulation means. In an electronic musical instrument that generates a musical sound waveform whose envelope changes asynchronously with the basic waveform, the status management means must be set to at least one of the set number and each envelope value/status.
This electronic musical instrument is characterized in that it generates musical sound waveforms omitting individual statasts.

The present invention will be described in detail below with reference to the drawings.

In the conventional method described above, multiplication and accumulation with new envelope values are performed correctly after the time of change. However, the values that have already been output but have already been accumulated are those that use the old envelope values, and those values and the new envelop 1. A problem arises in that the above-mentioned DC component is generated due to the accumulation of the multiplication results of J-B values.

The principle of the present invention is to add a correction value to the old accumulated value mentioned above so that the accumulated value becomes the new envelope value. 111
It is something to correct.

The above-mentioned DC component value Er is expressed as a function of the waveform differential value Δ, the envelope after change (i^n, and the envelope value O before change), and is expressed as −Er−ΣΔx (n−〇＞ ...(1) Here, the change in envelope value G!envelope cross IE V CK changes by only ±1) and -Ii, r -±ΣΔ (21).

Zuna:I)'ri,'4r:The principle of the invention is that the change in the envelope value with respect to EVCK is ±1, and ΣΔ is calculated in advance, and when the envelope value changes. Then, the ΣΔ at that time is added as a correction value for correction.

FIGS. 2 and 3 show waveform diagrams of a conventional system and a waveform diagram of the present invention, respectively.

Figure 2 (b) and Figure 3 (b) are waveform data, and Figure 2 (a) and Figure 31 (-) are the accumulated values, and the 1 cope value is added to the output. This is the musical sound waveform when it is set to 1.

Also, FIG. 3 (2) shows the digital values at that time. This value is the aforementioned ΣΔ, and if the en-rope value changes as shown in Figures 2(C) and 3(dl), the musical sound waveform at that time will be as shown in Figures 2(d) and 3(dl). It becomes as shown in Fig. 3 f).

In the conventional method, as shown in FIG. 2 (di), a DC component remains in the final value, but in the present invention, the DC component is corrected to -C as shown in FIG. 3 (i8). Of course, this is because when the envelope value changes asynchronously, it is corrected by adding the ΣΔ at that time.
Step S i''P in FIG. 3 (not shown) is the step resulting from this correction.

FIG. 4 shows a circuit diagram of an embodiment of the present invention.

Note that the same symbols as the conventional symbols described above are used for signals and the like. Scale clock generation circuit 1. status counter 2,
Envelope counter 3I enherobe clotho'
-1=Circuit 4 connects to processor CPU. Scale I
:l, the output of EXC of the check generating circuit 1 is input to the first input terminal of the gate circuit G1 and the gate circuit G1, and the +1 input terminal of the address counter 5. The 5YNC output of the address counter is the DC correction circuit 6. Enherobek 1 cock prohibited times vP17.

Input to the 5YNC input terminal of the attack synchronization section 8.

Note that the attack synchronization section 8. The connection of 5YNC input to the enrove clock inhibiting circuit 7 is omitted in the figure. One address output anchor of the address counter 5 is connected to the address terminal A of the differential value waveform memory 9. Its output is the multiplication circuit 10. It is input to the DC correction circuit 6. The attack synchronizer 8 further receives an attack-on signal '4AT ON, and its output is input to the status counter 2.

The AT output terminal of the status counter 2 is connected to the first input terminal of the OR circuit OR. The RL output terminal is connected to the second input terminal of the aforementioned OR circuit OR, the DC correction circuit 6° envelope counter 3. Or time 1? The output of &OR is input to the second input terminal of the AND circuit AND, and its output is input to the DC correction circuit 6.

The DC output terminal of status counter 2 indicates the number of ball 1 times 1.
Hall 1' terminal of i'&ll, stop signal ST&l) child is envelope clock inhibition circuit 7. The signals are respectively input to the correction prohibition circuit 12. The correction data of the DC correction circuit 6 is input to the first addition input terminal of the addition circuit 13 via the gate circuit G2. The output of the envelope 1 cope counter 3 is the bold circuit F1811, the multiplication circuit IO, and the gate circuit G.
1 to the second addition input terminal of the addition circuit 13. Further, the carry output of the envelope counter 3 is input to the status counter 2. The envelope clock of the envelope clock generation circuit 4 is input to the encoder L:I.
- input to the clock inhibition circuit 7, and its output is the envelope 1
It is input to the cope counter 3 and the correction prohibition circuit 12. The 1-coup clock output of the correction ratio 1/812 is input to the gate input of the gate circuit G2. The output of the adder circuit 13 is input to the cumulative q circuit 14. The output of the accumulator circuit 14 is connected to a digital-to-analog cog converter I)/A, not shown in FIG.

The operation of the embodiment of the present invention shown in FIG. 4 will be explained below using the timing chart 1 diagram shown in FIG.

The signal of the pressed key is detected by the processor CPU, and the data corresponding to the pressed key is sent to the scale clock generation circuit 1.
Enter. The scale I:J clock generation circuit 1 generates a timing clock I?of the clock corresponding to the data. , XC (FIG. 8(b)) are generated, and the data in the address counter 5 is incremented. The data of the address counter 5 is sequentially incremented by 1 in response to the timing clock EXC, and the address A of the differential value waveform memory 9 is
access.

It also generates a synchronizing signal 5YNC (FIG. 8 (cl)).

The synchronization signal 5YNC is a carry of the address counter 5, and is a signal that does not indicate that the contents of the address counter 5 newly start from 0. The differential value waveform memory 9 outputs the memory data specified by the address counter 5 mentioned above. The data stored in the differential value waveform memory 9 (
Figure 8(a)) shows the differential value of the musical tone, D C? 11i
Input to the positive circuit 61 multiplication circuits 11 & 10. The attack synchronizer 8 receives the actu-on signal A i"I' ON (FIG. 8(f)), and changes the actuating signal ATT (FIG. 8(g)) to the status in synchronization with the next synchronizing signal SYNC. Output to counter 2.

Status counter 2 receives the carry output of envelope counter 3, that is, status change January (Fig. 8).
kl) and attack AT, degai l)C,
Outputs each status signal of release RL. Figure 8 (
1,1 AT those status.

They are indicated by DC and RL, respectively. Note that BP is a status that does not succumb to the above-mentioned statuses, and indicates that the status counter 2 is empty (blank). Also,
The status counter 2 also outputs a stop signal ST. This signal is input to the envelope clock inhibiting circuit 7, and becomes a control signal for outputting the envelope clock II, , or not (eighth output)). En to 1: 1-puku l'tsuk generation circuit 4 is a circuit that generates en to 1'-pukuronok E V CK, and en to 1'-pukuronok defined by pu1'se,su CI) U. EVCK (Fig. 8 (It
) 'cx 7 heo -7' black,.

A signal is sent to the inhibition circuit 7. En to τ:? - In the stop check circuit 7, the envelope check EV generated in the stop check generation circuit 4 generated by the status counter 2
Decide whether to prohibit C l<. FIG. 8 (Jl indicates the signal E V C K
K The envelope counter 3 is a circuit that forms a :1-nin rope waveform according to instructions from the processor CPU, and counts the pulses of IVCKX at the same time as the attack AT. Further, the pulses of EvcKx are counted also during degay DC. The release RL of status counter 2 is +/++Ij. of envelope counter 3. 1
When the envelope counter 3 is released RL, the envelope counter 3 performs a decrement operation from the maximum value of the envelope counter 3 in the opposite manner to that described above. The output of the envelope counter 3 is input to the bold circuit 11, and when it is attack AT or release RL, it passes through the bold circuit 11 and is input to the multiplication circuit 1.
Enter o. Decay I) At the time of C, the maximum value of the envelope counter 3, that is, the final value of the attack AT, is bolded by the bold circuit 11 and input to the multiplication circuit 1o. This hold circuit 1' is a circuit for holding the maximum value of the envelope at the time of self-decay DC,
Since the envelope counter 3 counts even during decay DC, this circuit prevents this value from being input to the multiplication circuit 1o. The multiplication circuit 1o is a circuit that multiplies the data of the differential value waveform memory 9 and the data of the bold circuit 11, and outputs the differential value of the musical tone waveform to 7 corresponding to the envelope buoy 1N. The value is input to the adder circuit 13 via the gate 11/It Gl, but the gate of the first gate G1 is turned on by the timing clock EXC, and the value is input to the adder circuit 13 at the timing of the timing clock EXC. do.

On the other hand, OR circuit OR is attack A'F and release R1
We are finding the logical OR of each state of , and the attack Δ1゛,
When the release R is somewhere between RL and RL, the gate of the AND circuit ΔND is turned on, and a timing signal is input to the DC correction circuit 6 (FIG. 8 (ttl)).

This is because there is no need for correction when using Degay DC, and other than that, attack A'F, release RL
A correction value is determined only when .

The DC correction circuit 6 also receives a synchronization signal SYNC. This is D when the address counter reaches zero.
This is to clear the contents of the C correction circuit 6 at the same time. That is, in the DC correction circuit 6, i
The data M is accumulated only at the time of AT and release RL, and the value is input to the adder circuit 13 via the gate circuit G2, but the accumulation is performed using the timing clock EXC.
This is done by the +111 signal SYNC and is constantly cleared in units of one period of musical tone. ? TS 8 (di indicates the correction value of the DC correction circuit 6.

In the present invention, correction is not performed at the time the status changes. The correction prohibition circuit 12 and the gate circuit G2 prohibit this correction.

The correction inhibition circuit 12 does not output EVCKX when the stop signal ST obtained from the status counter 2 is at H level, but outputs it when it is at L level.

The output of the correction prohibition circuit 12 is input to the gate circuit G2, and
It controls whether or not the correction value of the C correction circuit 6 is input to the addition circuit 13. That is, the gate is turned on only when the clock is output from the correction prohibition circuit 12, and the DC correction circuit [
The correction values of 1 & 6 are input to the addition circuit 13. Addition circuit 1
3, the differential value of the musical tone related to the envelope value input via the gate circuit G1 and the gate circuit G2 and the correction value of the DC correction circuit 1zPf6 are added and outputted to the accumulator circuit 14.

The output of the adder circuit 13 is the sum of the differential value and correction value of the musical tone corresponding to each clock, and the value is accumulated in the accumulator circuit 14. Although not shown in the embodiment of the present invention shown in FIG. 4, the output is the digital-analog 1. The signal is input to the J/G converter RI/A, becomes an analog signal, and is output as a musical tone from a speaker via an amplifier. Figure 8+nl 4
The output waveform of the J digital-to-analog conversion circuit is shown. As is clear from this waveform, there is no change in the DC component.

FIG. 5 shows a circuit diagram of the attack synchronization section 8. The actuon signal Δ'I''TON enters the OR circuit 01, and its output is input to each input of the AN1' circuit ANI and AN2.The output of the AND circuit ANI is input to the OR circuit 01 via the register R1. , the synchronizing signal 5YNC is input to the AND circuit AN2, and its output is the actuating signal ATT.
It is output to the status counter 2 as a signal and is also input to the AND circuit ANI via the inverter r1. OR circuit 01. The AND circuit ANI and the register R1 form a loop, and the signal of the actuator ON signal ATi'ON is written in this loop. However, when the attack on signal A T TON is input, the loop becomes 1.
■Rehel is activated, and the gate AND circuit AN2 is turned on. As a result, the synchronizing signal 5YNC of the method is outputted as an attack signal AT T via the AND circuit AN2, and is also input to the AND circuit AN2 via the inverter 11.
Set the loop level to L level.

FIG. 6 shows respective circuit diagrams of the DC correction circuit Il&6 and the gate circuit G2. The output of the AND circuit AND is commonly input to the first gates of the ant circuits AN3 to AN6. Also, the differential value from the differential value waveform memory 9 is input to the second gates of the second gate circuits 3 to 8N6. )' The outputs of the AND circuits 3 to AN6 are exclusive logic logic j'120
It is inputted to the addition input BO-83 of the 6-bit serial number A via R1-EOR4. - The release RL of the power and status counter 2 and the minus signal of the differential value waveform memory 9 are input to the exclusive logic OR EOR5, and the signal is input to the carry power Cj and the exclusive logic OR EOR1~E.
○R4 and full adder FA addition input B4. Enter in B5. Synchronous signal 5YNC is reset 1 of registers R2 to R7
Input to one terminal input. Full adder FA addition signal SO
The addition signal S5 is input to the input of the register R2-1-7, and its output is connected to the AND circuits AN7-ANI2 and the augends AO-Δ5 to the full adder F. In addition, the other gate of the AND circuits AN7 to AN12 is the correction prohibition circuit 1.
The two outputs are connected in common, and the output is input to the adder circuit 13. The antenna circuits AN7 to AN12 are the gate circuit G2 shown in FIG. The signal input from the differential value waveform memory 9 is inputted via the AND circuit AND, and then un+ times [?] by the Dock King XC. & A.N.
The gates of 3 to AN6 are turned on, and the exclusive logic OR I
', ORI~IE It is added to the full adder F via OR4 with the values stored in registers R2~R7. The result is output from the addition signal S(]~S5 and stored again in the registers R2~R7.Exclusive logical OR EOR
The output of 5 is a signal specifying addition or subtraction, and when the output is at H level, it is a subtraction operation, and when it is at I-level, it is an addition operation.

Full adder F is an adder, but addition inputs BO to B3
Depending on the conditions, a two's complement number may be created by exclusive logical ORs EOR1 to EOR4 connected to EOR1 to EOR4.

In this case, it is a subtraction. AT AT and release R
In the case of L, since the value to be corrected is reversed in positive and negative, the processing is determined by the exclusive OR of the release RL and the differential value waveform memory 9 in the case of 1 no [alternative logic OR EOR5. That is, in the release RL state, the output of the exclusive OR EOR5 becomes an addition signal - when the data in the differential value waveform memory 9 is negative, and becomes a subtraction signal when it is positive.

In addition, when the data in the differential value waveform memory 9 is negative when not in the release RL state, it becomes a subtraction signal.
When it is positive, it becomes an addition signal.

Register R2 where the addition result of full adder I/Δ is stored
~R7 has a tone waveform value when the envelope value is 1, but its sign is, as mentioned above, release I?
When it is L, the situation is reversed. Resetting registers R2 to R7 61! The synchronizing signal 5YNC input to the l register resets the registers R2 to R7 at one cycle of the musical tone, and this means that the data stored in the registers R2 to R7 has positive and negative directions depending on the status. A synchronization signal 5YNC is input to synchronize them.

FIG. A circuit diagram of the correction prohibition circuit 12 is shown. The envelope clock EVCK of the envelope clock generation circuit 4 is an AND circuit A.
input to the first input of N13.

On the other hand, the synchronization signal 5YNC is set reset flip 1
Kotops R1? The output Q is input to the second input of the AND circuit AN13. The output of AND circuit AN13, that is, EVCKX
is input to the envelope counter 3 and the AND circuit AN14 of the correction inhibition circuit 12. A stop signal; 8J-8'F is also input to the AND circuit ANI4 via an inverter I2, and its output is input to the gate circuit G2 via a register R8. When the stop signal ST is input, the center reset flip-flop 5RFF is reset and the envelope 1 copy clock EVCK input to the AND circuit ΔN13 is no longer output. When the synchronizing signal 5YNC is input next to the stop signal ST, the 7-stripes 5RFF is sent, the output becomes 1, and the AND circuit AN13 is turned on to turn on the envelope clock.
EVCK is output. Zunawarago signal station EVC
KX, which is input to envelope count;l and also input to AN14. The reset flip-flop 5RFF is stored in the system clock φS, and even if the stop signal ST is input, the envelope clock EVCK at that time is outputted via the AND circuit AN13. Envelope clock E at this time
There is a correction prohibition circuit 12 mode that prohibits VCK.
'Circuit AN14 outputs stop signal ST inverter 1-i
is turned off by B-1g, and at this time register R8
IE V CK X is not manually operated. Figure 8 fml
is a correction enable signal input to gate [ian/&c2. In FIG. 8h+, the clocks marked with an x mark are prohibited from being corrected by the correction prohibition circuit 12.

FIG. 9 and FIG. 1O show timing charts of the embodiment of the present invention shown in FIG. 4.

? (The timing chart shown in Figure 58 shows that the envelope status is l!, VST is A'F,
In the case where it changes to Decay DC and Release RL,
? (In figure S9, if there is no status of AC AT, then in Figure 1θ, AC AT, Decay DC
This is the case when both statuses do not exist.

Of course, Fig. 9 shows the actu-on signal A i”T O
Due to H, the ac/7 signal ATT generated by the next synchronization signal 5YNC causes the degay DC state, and then the release RL
This shows the case where the condition occurs. In addition, FIG. 10 shows that the next synchronizing signal 5YN is activated by the actu-on signal AT T ON.
This shows the case where the release RL state is reached by the ACK signal ATT generated at C.

FIG. 9 will be explained in more detail.

By inputting the add-on signal 8'T'T ON, the actuating signal AT is activated in synchronization with the synchronizing signal 5YNC.
T is generated from the attack synchronization section 8. Due to this signal, the envelope status E V S 'l'' becomes a digay DC, and the width of one axis of the output waveform becomes 7. Note that the maximum envelope value EV is 7) (Fig. 9).

In FIG. 10, it is set to 7. Since the envelope value EV before the change is set to zero, no correction is necessary at this time. Since there is no change in amplitude during decay DC, correction is prohibited. Next, Decay DC changes to Lease RL state,
Correction is made in this state. Of course, the correction value is subtracted from the waveform value every time the envelope value EV changes asynchronously with the synchronization signal 5YNC.

The operation in FIG. 10 is the same as that in FIG. 9.

However, in Figure 1θ, attack AT and decay DC
There is no release RL, so start from release RL. However, when the attack on signal ATTON is input, the attack signal ATT is generated from the attack synchronization signal 81 (8) in synchronization with the synchronization signal SYNC.

Due to this signal, the envelope status EVST becomes release RL, and the amplitude of the output waveform becomes 7. but,
Since this state is release RL, the envelope value E
A correction value is subtracted from the waveform value every time V changes asynchronously with the synchronization signal 5YNC.

The present invention has been described in detail above using examples.

According to the present invention, the envelope can be changed many times in one cycle of the musical sound waveform, and even if the envelope is changed rapidly, no DC component remains, producing a sound that is closer to the musical tone of the musical instrument. It is possible to generate all the F11 child instruments.

Furthermore, according to the present invention, attack AT, degay 1) C,
It is possible to generate a musical sound waveform in which at least one status of each status such as release RI- is omitted.

In addition, in the embodiment of the present invention, registers RO to l?
+1 is a bit register operated by the system J2 clock φS, but this uses a multi-bit shift register. This allows multiple sounds to be generated simultaneously.

Furthermore, in the embodiment of the present invention, the change in envelope value is ±1
I explained it as, but this. By multiplying the output of the DC correction circuit by the change value, it is possible to increase it to 2.3...

[Brief explanation of the drawing]

FIG. 1 is a quimming chart diagram of a conventional electronic musical instrument, where (al is a timing clock, (bl is a synchronization signal, f
c) is the attack signal, fdl, (h) is the envelope clock, +e+, (11 is the envelope value, (fl
, (Jl is envelope status, tg), (
kl each indicates a musical sound waveform. Fig. 2 is a basic waveform diagram of a conventional electronic musical instrument, Fig. 3 is a basic waveform diagram of an electronic musical instrument of the present invention, Fig. 4 is a circuit configuration diagram of an actual JAii example of the present invention, and Fig. 5 is a basic waveform diagram of a conventional electronic musical instrument.
7 to 7 are circuit diagrams thereof, and FIGS. 8 to 10 are timing charts of the electronic musical instrument of the present invention, where ta+ is a waveform differential value, (I)) is a timing clock, and tc+ is a synchronization signal. , (di is the correction value, (e+ is the gate signal, (fl
is the actuon signal, tg) is the attack signal, (h) is the control signal for outputting the envelope clock, (
11, (Jl indicates the engine clock, (1c) indicates the status change signal, (1) indicates the envelope status, (m+ indicates the correction enable signal, and (fl) indicates the musical sound waveform. ■... Scale Clock generation circuit, 2... Stake counter, 3... Envelope clock, 4.
...Envelope clock generation circuit, 5...Alles counter, 6...DC correction 1ii1178, 7
...Envelope crotch inhibition circuit, 1 (...attack synchronization section, 9t...differential value waveform memory, 10
...Multiplication circuit, 11...Circuit for Pohar,
12...Correction inhibition circuit, 13...Additional circuit,
14... Accumulation circuit, CI) (J... Procenoza,
Gl, G2...Gate times 1, OR, 01...
OR circuit, AND. ANI~AN14...AND circuit, R1-R8...
・l/Register 11, 12... Invar/Yu,
EORI~EOR5...Exclusive logical OR, FA...
Full adder, 5RFF...Sesotorisesotofurisopfurosop. Patent 11) 11 people Casio Computer Co., Ltd. Agent R Physician Yoshiyuki Suga Figure 2 Figure 3

Claims (2)

[Claims] (1) A first slope generation means for generating a scale clock corresponding to the pressed key, a memory storing differential data of the fundamental waveform, and generating an enherobutton lock corresponding to the pressed key. a resulting second multiplier 1:I clock generation means, and a multiplier circuit for multiplying the data read from the contents of the memory in relation to the first clock generation means by an envelope value in relation to the second clock generation means. and an IH current correction circuit, an addition circuit for adding the output of the multiplication circuit and the output of the DC correction circuit, and an accumulation means for accumulating the output of the addition circuit, the accumulation means comprising: In an electronic musical instrument that generates musical waveforms whose envelopes change asynchronously with the basic waveform by digital-to-analog converting means, a status management means is provided, and at least one of the envelope statuses of each envelope status is specified.II? An electronic musical instrument characterized by generating a musical sound waveform omitting the l+ status. (2) The electronic musical instrument according to claim 1, wherein the status management means comprises a counter, and the counter has a function of skipping at least 11 status lists among each envelope status.