JPS5924327A - Decentralized priority selecting device - Google Patents

Abstract

PURPOSE:To realize disconnection or connection without changing the constitution, by providing a signal showing whether a circuit is incorporated into a daisy chain for each circuit to be incorporated into the daisy chain and then informing the generation of the above-mentioned signal to the following circuit. CONSTITUTION:When priority selecting circuits 2, 3 and 4 are all packaged, the gate terminals of tri-state gates 9B and 9C are set at L with the output set under a high impedance state since a terminal of each of lead wires 10A, 10B and 10C is converted into an earth. While the gate terminals of tri-state gates 8B and 8C are inverted to H, and therefore the logic of a normal input signal is delivered as it is. Then the circuit 2, for example, is taken out, and the wire 10A is cut off and a terminal of the wire 10A is released from the earth. Then the gate 9B delivers the input signal of that time point as it is. Thus the circuit 3 is set at the highest place, and the circuit 4 follows the circuit 3 in a new form of a daisy chain.

Description

[Detailed description of the invention] The present invention relates to a distributed priority selection device.

In a system in which a plurality of devices use a common bus, there are conventionally two methods for determining the priority order for use of the common bus. The first is to provide a priority selection circuit at one location common to all devices, and the second is to provide a priority selection circuit for each device. The second method is widely used because the logic and structure within the circuit are simple.

The second method is also called the distributed priority selection circuit method,
The priority selection circuits for each device are configured to be connected in series, and the priority order is determined based on the order of the series connection. However, in the distributed priority selection circuit system, the control lines of each circuit are connected in series. There is a drawback in that it is necessary to change the connection of control lines when installing. 'In Figure 1,
A connection diagram of a conventional daisy chain type distributed priority selection circuit is shown. Processor l has each priority selection circuit 2, 3
．． It takes in the ■ signal and the BGACK signal from 4, and sends out the surface signal to the selection circuit 2. The BG signal is sent through the upstream priority selection circuits 2→3→4 in a daisy chain manner.

Here, the signal enabled means the bus occupancy request signal (BUSRKQ).
The selection circuits 2, 3.4 each independently generate a bus occupancy request signal. However, when bait-1, there is a bus occupancy request, and by reversing this, it becomes BR-0. The signal enable signal is a bus occupancy grant signal (BUS GRANT signal) from the processor 1 in response to a surface signal. The BGACK signal is a signal generated after receiving the enable signal from the selection circuit that issued the previous bus occupancy request signal, and is a response signal.

In addition, the ■ signal and BGACK signal for each selection circuit are BRO
, BIT Engineering, BR2, IIGACKg, BGAC
KI, BGACK2.

Each selection circuit 2, 3.4 is connected to various terminal devices (not shown).
and forms an interface with processor l when the bus is occupied. Among the selection circuits 2.3.4, the occupancy requests have different priorities, and the order is (selection circuit 2)>(selection circuit 3) (selection circuit 4). According to the connection order of this priority daisy chain, the upstream side is the upper one and the downstream side is the lower one.

Each priority selection circuit 2, 3, 41-J:, inverter 5A.

5 Summer 3, 5C, Nando' Gate 6A, 6B, 6
C, oven collector output and gate 7AA, 7
AB, 7BA.

It consists of 78B, 7CA, and 7CB. The daisy chain has a thread path of 5A→6B→5C→6C. The outputs of AND gates 7AA, 7BA, and 7CA form wired OR, and AND gates 7AB and 7
The outputs of 8B and 7CB form a wired OR.

FIG. 2 shows an operation time chart of the processor J and the selection circuit. When a common bus occupancy request occurs in any one of the priority selection circuits 2, 3.4, an occupancy request signal head is sent to the processor 1 via the wired OR described above. Processor l takes in the occupancy request (plane i), then determines whether or not occupancy should be granted, and when occupancy should be granted, sends an occupancy permission signal BGf to the highest priority selection circuit 2. This occupancy permission signal layer is sent out one after another in a daisy chain from upstream to downstream via the priority selection circuit. The priority selection circuit that generated the previous bus occupancy request signal basket takes in the BG signal. The enable signal is not sent to the downstream priority selection circuit after this priority selection circuit, and the downstream priority selection circuit is not allowed to occupy the bus. As a result, bus occupancy request signals BR (BRo, BRI, BR
Even if I) occurs, only the highest priority selection circuit among the priority selection circuits that have generated the occupancy request signal achieves bus occupancy.

Through the above process, the right to use the bus can be determined.

In the next step, the priority selection circuit that has determined the occupancy is interposed between the processor 1 and the terminal, or the processor 1 and the terminal use the necessary bus without intervening.

In the above Ha configuration, if the priority selection circuit 2 or 3 is disconnected from the circuit for some reason, the enable signal from the processor 1 cannot be transmitted, and a new connection change is required. Further, after this connection change, connection changes are also required when returning and mounting the circuit 2 or 3.

An object of the present invention is to provide a distributed priority selection device that enables disconnection from a daisy chain or insertion of a new device into the middle of a daisy chain without changing the connection of the daisy chain.

The gist of the present invention is that each circuit incorporated into the daisy chain generates a signal indicating whether or not it is incorporated into the daisy chain, and this signal is communicated to the subsequent circuit. In addition to the signal indicating the presence or absence of integration, the circuit at the subsequent stage takes in the signalable signal from the previous stage in the same manner as in the conventional daisy chain method, and determines whether or not there is integration from the signal indicating the presence or absence of integration and the signalable signal from the previous stage. Self-imports surface signals. This created a bypass system.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of the priority selection device of the present invention. Each priority selection circuit 2, 3.4 includes negative dry state gates 8A, 8B, 8C, positive tri-state gates 1-9A, 9B, -9C, and inverter 5.
A.

5B, 5C, Nantes Gate 6A, 6B, 6C,
Open collector output andchi) 7AA, 7A
B, 7BA.

It consists of 78B, 7CA, and 7CB. Furthermore, each priority selection circuit 2, 3.4 has a lead wire 1 whose one end is grounded and carries a signal FPE indicating the presence or absence of disconnection.
It has 0A, 101'3, and IOc, and is connected to the gate terminal G of the next stage tristate gates 80, 8C, 9B, and 9C.

negative dry state game) 8A, 8B,
The logic of 8C is that when the signal to the gate terminal G is L, the logic signal of the regular input signal (1# or 10I) is output as is, and when the signal to the gate terminal )8A
, 8B, and 8C are in the output high impedance state (Z). The logic of the positive tristate gates 9A, 9B, and 9C is such that when the signal to the gate terminal G is H, the logic signal of the normal input signal (
%lI or 'o') is output as is, and the gate terminal G
When the signal to the gates is L, the gates 9A, 9B, 9G
This is the logic that makes the output of FM(,Z) high impedance.

Open collector landlock)・7AA, 713A
.

The output of 7CA is a wired OR (1 signal), and the n signal is output to processor 1. Each is connected to optical selection circuit 2.
Among them, the signals 13RQ, BRI, and plane 2 are generated separately, or two or three of them may occur simultaneously. When a plurality of signals occur simultaneously, in a general TTL output circuit, an unnecessary flow occurs in each circuit, making wired logic impossible. Another method is to use a tri-state gate, but it is prohibited to use it in such a way that the gates of multiple elements are opened at the same time. This is because it is considered to be the cause of IC deterioration and failure. For the above reasons, open collector gates 7AA, 7BA, and 7CA are used for outputting surface signals. Other open collector circuits (7AB, 78B, and 7CH) are also used for outputting the BGACK signal for a similar reason.

In the above configuration, assuming that all of the priority selection circuits 2.3.4 are implemented, the lead 11OA.

One end of JOB and IOc is grounded and is logically L. Therefore, dry state game) 9B.

The gate terminal of 9C becomes L, making the output high impedance state. In this case, each dry state game) 9
B, the logic of the normal input signal to 9C (%ll75=
'o') is not transmitted to the output side. On the other hand, the gate terminals of the tristate gates 813 and 8C are 1 because L is inverted and becomes II. iE standard input signal logic (
11# or Of) is output without changing it. As a result of the above, when all the housing head selection circuits 2, 3, and 4 are connected, a daisy chain is formed in the circuit shown in FIG. 1 for every song. Therefore, the method of priority selection is also the same as before.

Next, when one of the priority selection circuits, for example, priority selection circuit 2, is removed, the lead wire 10A is disconnected, and one end thereof becomes open from the ground. When this open state is considered to be H, the tri-state gate 8B becomes a high impedance output, and the dry state gate 9B becomes a logic state in which it outputs the input signal at that time as it is. At this time, the input to the dry state gate 9B is the correction signal itself, and this 1 forms the bypass thread path. Therefore,
Priority selection circuit 3 is on the top level, priority selection circuit 4 is on the next stage.
This results in the formation of a new daisy chain where .

The above explanation is about removing the priority selection circuit 2, but the same relationship holds true when removing the priority selection circuit at any position except the priority selection circuit at the last stage of the daisy chain.
Automatic daisy chain formation. Furthermore, when re-implementing the priority selection circuit once removed on the circuit,
By grounding the appropriate lead wire, the original dietche f formation is obtained.

FIG. 4 is a diagram showing another embodiment of the present invention. Priority selection circuit 2
0, 30, 40U ear bar 120A, 30A
, 40A anime) 20B, 20C, 3013
, 30C, 40B, 40C.

OR gate 20D, 30D, 40D1 inverter 20E.

It consists of lead wires 3QE, 40E, and lead wires 20F, 30F, and 40F, each end of which is grounded. Processor l is omitted in the drawing. The priority order is (priority selection circuit 20) > (priority selection circuit 30) > (priority selection circuit 40).

Whether the output of inverter 2OA, 30A, 40A is gate 20B or 20C, 30B or 30C, 40B or 4
Select between 0C and 0C. Goo) 2011, 30B,
40B are the output inverters (20F, 30E) of the previous stage birth selection circuit, respectively.

Input the output of 40E into gate 20C,
C.

40C is the output inverter (2
(equivalent to 0E, 30F, 40E). Each output inverter 21, 30E, 40E receives the output of the OR gate 20D, 30D, 401). Furthermore, inverters 2OA, 30A, 4
0A is the lead terminal (20F,
30F, 40F) output and all inputs.

In the above priority selection circuits 20, 30, and 40, the path occupancy request signal layer and the BG response I/A 13GAcI (sending path) are omitted.Furthermore, the interface with the processor is omitted.The reason is as follows. These points are not particularly different from those shown in FIG. 3, and only the transmission system of the occupancy permission signal box is different from that shown in FIG.

In the above configuration, if all of the priority selection circuits 20, 30, and 40 are mounted with their wires connected, the circuits 20C, 30C, and 40C remain off.

On the other hand, the inverters 20E, 30F of the priority selection circuit of the i'iiJ stage are turned on.

The output of 40E is inverted and output. This means that a daisy chain is formed, and the priority selection circuit is selected in the same way as in FIG.

On the other hand, if you remove the priority selection circuit, for example, the eggplant, lead wire 2
One end of 0F is in an open state, and in this open state, if the lead wire 20F has a potential of II level, the antagonal gates 30B of the priority selection circuit 30 are turned off. On the other hand, Antogame) 30C passes the output of the output inverter of the priority selection circuit in the two previous stages, so that the priority selection circuit in the two previous stages → priority selection circuit 30 → (priority selection circuit 40 →
A daisy chain path is formed. As a result, even if the priority selection circuit is removed, the remaining circuits do not form a daisy chain, and the work of configuring one daisy chain becomes unnecessary.

According to the present invention, in a daisy chain composed of a plurality of devices using a common bus, a device in the middle of the daisy chain can be removed from the daisy chain! 2J away, no special configuration changes are required when entering a new connection. Therefore, there is an advantage that the device can be easily repaired and expanded.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional example, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a diagram of an embodiment of the present invention, and FIG. 4 is a diagram of another embodiment of the present invention. 1... Processor, 2, 3.4... Priority selection circuit,
8A, 8B, 8C... Negative tristate gate, 9A, 9B, 9C... Positive tristate gate, 10A, IOB
, IOC... lead wire. Agent Patent Attorney Tadashi Akiki Figure 1 Figure 2

Claims (1)

[Claims] Consisting of a processor and a plurality of priority selection circuits, each priority selection circuit sends a bus request signal for use of a common bus to the processor, and receives a bus occupancy permission signal from the processor.
When there is no occupancy request in the upstream priority selection circuit, the bus occupancy permission signal is received via the upstream priority selection circuit, and only when the own priority selection circuit is issuing an occupancy request, the bus occupancy permission signal is received from the upstream side, and the bus occupancy permission signal from the downstream side is received. In a distributed priority selection device that is locked to prevent the bus occupancy signal from being generated to the priority selection circuit, each priority selection circuit is configured as a system in the same way as other priority selection circuits. A signal line is provided to indicate whether or not it is connected as an element, and when the signal level of the signal line is considered to be disconnected from the main system, the connection with the priority selection circuit directly preceding and succeeding the own priority selection circuit is determined. A distributed priority selection device formed by forming a transmission path for a bus occupancy permission signal between the two buses.