JPS5897726A - Priority controller - Google Patents

Abstract

PURPOSE:To perform the quick decision and control of a process request, by dividing numbers of input/output devices into plural groups and providing the group busy lines in accordance with the priority among the groups. CONSTITUTION:An FF9 is set by a either one of input/output devices IOC211, 212 and 213, the signal logic on a group busy line 14 is set at 0 via a group busy signal tansmitting circuit 16. Under such conditions, it is inhibited that an AND gate 10 of an IOC of another group is set at an output 1. In such a way, the signal is delivered to the line 14 via just one step of the circuit 16 when either FF9 is reset. As a result, the time during which the next acknowledge signal line 4 is actuated from a CPU1 can be greatly decreased. Thus the transfer capacity of data can be improved.

Description

[Detailed Description of the Invention] This invention provides a large number of input/output casings (hereinafter abbreviated as IOC).
This relates to priority determination control of processing requests to a central processing unit (hereinafter abbreviated as CPU).

A conventional device of this type is shown in FIG. In Figure 1, (1) is the CPU, and (2) is the IOC.
A common request signal line (3), acknowledge signal line (4), and data line (5) are provided between the CPU (11 and each IOC<2'>, and each IOCf2)
The terminals are connected by a priority signal line (6) in a straight-line manner.

Also, FIG. 2 is a connection diagram showing the internal connections and interconnections of the l0C(2), in which the same reference numerals as in FIG. 1 indicate the same parts. , (8) is a priority signal transmission circuit composed of a Nant gate, (9) is a request flip-flop (hereinafter abbreviated as FF), and the set/reset input signal circuit of FF (9) is omitted in this drawing.
(10 is an AND gate, αchin is a data register, (6)
is a request signal transmission circuit consisting of an inverter,
(to) is a data transfer enable signal. Although the internal connections of each IOC (2) are the same, parts unnecessary for explanation are omitted in the drawings.

Next, the operation will be explained. The IOC (2) that has generated a processing request for the CPU (11) sets its FF (9). The logic of the Q terminal of the FF (9) becomes "1" K, and the request signal is transmitted via the request signal transmission circuit (6). The signal logic on the line (3) is set to 0 to notify the CPU (1) that a processing request has occurred.The logic of the Q terminal of the FF (9) is transferred from the signal transmission circuit (8) to the priority signal line (6). ), the output of the priority signal receiving circuit (7) becomes a logic rOJ, and the output of the transmitting circuit (8), which takes this output, becomes a logic "1". (The output of 10 is prohibited from becoming logic ``1'', so FF(9)
If there are multiple IOCs (2) issuing processing requests by setting , the priority signal line (6
) all signal logics above become "1".

The CPU (1) has the logic on the request signal line (3) r
OJ, at least one IOC(2)OFF(9
) is set, and connects the acknowledge signal line (
4) Send a logic "1" signal on the top. If the output of the priority signal receiving circuit (7) is logic "1" and the output of the Q terminal of F F (9) is logic "1", then
A signal from 0 to logic “1” (to) is output, and this signal α
3, the contents of data register αυ become data line (5)
After this operation is completed, the FF (9) is reset. When the FF (9) is reset, as long as the output of the priority signal receiving circuit (7) is logic "1", the output of the priority signal transmitting circuit (8) becomes logic "o", which is the output logic of the AND gate αO in the subsequent stage. gives an opportunity to become "1" K. Therefore, between multiple IOCs (2) that have set F F (9), the one whose input signal to the priority signal receiving circuit (7) is logic "0" has the right to perform the next data transfer. Thus, priority control is performed by the priority signal line (6).

Since the conventional priority control device is configured as described above, the signal is transmitted from the priority signal line (6) to the priority signal receiving circuit (7) to the priority signal transmitting circuit (
8) → It takes a considerable amount of time to be sequentially transmitted through the priority signal line (6) and reach the final stage IOC (2), and this time increases as the total number of cascaded IOCs (2) increases. , all priority signal lines (6)
Since the CPU (1) cannot output a signal on the acknowledge signal line (4) until the signal logic of
This has the disadvantage of reducing overall processing speed.

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional ones, and an object of the present invention is to provide a control device that can perform priority determination control at high speed. For this purpose, the present invention divides a large number of IOCs into a plurality of groups, determines in advance the priority order between groups and the priority order among IOCs within the same group, and sends a priority signal to all IOCs [transmitted]. Reduced the time required.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or corresponding parts, (211)
, (212), (213) are the IOCs in the first group, (221), (222), (22
3) rig 2 +7) IOC belonging to rip
, (231), (232), and (233) are IOCs belonging to the third group, and the priority among the groups is 1st → f
jlL2 → 3rd rank, and the priority within each group is indicated by the code attached to the drawing ((211), (212)...
・etc.) α fathom is the group busy line of the first group, and (to) is the group busy line of the second group. Since the third group has the lowest priority, there is no need to issue a group busy signal. Figure 4 shows the internal connections of the IOCs belonging to the first group, Figure 5 shows the internal connections of the IOCs belonging to the second group, and Figure 6 shows the internal connections of the IOCs belonging to the third group. The same reference numerals as in FIGS. 2 and 3 indicate the same or corresponding parts, αQ.

αη is a group busy signal transmitting circuit each composed of an inverter. Also, in the case of the i@4 diagram, the AND gate 01 is powered by three people, similar to the case in Figure 2, but in the case of Figure 5, the group busy line Q4 is input in addition to the three humans, and in the case of Figure 6, the AND gate 01 is If so, please use the group busy line in addition to the above 3 people.4. (g) is input.

The operation of the circuit shown in FIG. 3 will be explained below with reference to FIGS. 4 to 6. IOC (211), (212),
(When FF (9) is set in any of 213, the group busy line α is transmitted through the group busy signal transmission circuit α→
Set the signal logic on 4 to "0". In this state, the output of the AND gate αQ in FIGS. 5 and 6 is prohibited from becoming a logic "1" trap. Also IOC (221), (222)
.

(223), when FF (9) is set, the group busy line (
To) K the upper signal logic to “0”. In this state, even if the signal logic on the group busy line α is "1", the output of the AND gate α4 in FIG. 6 is prohibited from becoming logic "1". Priority control between groups is performed as described above, and priority control within the same group is performed in the same manner as before.

Comparing the circuit in Figure 3 with the circuit in Figure 1, if the leftmost IOC (2) resets F F (9) in the circuit in Figure 1, the priority signal receiving circuit of the rightmost IOC (2) The output logic of (7) becomes “1” (0FF on the way)
(9) is all reset), along the priority signal line (6), there are 8 stages of priority signal transmission circuits (8) and 8 stages (of which 1 stage is in the IOC)
The signal propagation delay time is large because it has to go through the priority signal receiving circuit (7), but in the circuit shown in Figure 3, the IOC (211), (212), (213)
When any 0FF (9) of
The time required from the first acknowledge signal line (4) to operate the next acknowledge signal line (4) is significantly shortened, and the data transfer capacity can be improved. ! In the circuit shown in Figure 3, the total number of IOCs (2) connected in a fixed manner by the priority signal line (6) is 3, so IOCs (211) OF F (9)
After the IOC (213) is reset, until the output logic of the priority signal receiving circuit (7) of the Ioc (213) becomes "1", two stages of the priority signal transmitting circuit (8) and a two stage priority signal receiving circuit (7) are required. ), this is a significant improvement over the circuit shown in Figure 1.

Although the above embodiment shows a case where nine IOCs are divided into three groups of three IOCs, the number of groups and the number of IOCs belonging to each group can be arbitrarily selected. Furthermore, although Figures 4, 5, and 6 show cases in which the circuit configurations are different, it is also possible to make the circuit configurations of each group the same by separately providing an auxiliary circuit. It is also possible to change the group to which the IOC belongs or change the priority order between groups by changing the connection of the auxiliary circuit.

As described above, according to the present invention, a large number of IOCs are divided into a plurality of groups and group busy lines are provided according to the priority order between the groups, so that the priority determination control of processing requests can be performed more quickly than in the conventional device. This can significantly improve the overall data transfer capacity.

[Brief explanation of drawings]

Figure 1 is a block diagram showing a conventional device, Figure 2 t-1f
$, Figure 1 is a connection diagram showing connections within the input/output control device and between devices, Figure llEa is a block diagram showing an embodiment of the present invention, Figures 4, 5, and 6L are each @
FIG. 4 is a connection diagram showing connections within the input/output control devices belonging to the first, second, and third groups in FIG. 3; (1)...CPU, (211), (212), (2
13)...IOCs belonging to the first group,
(221), (222), (223)... IOCs, (231) each belonging to the second group. (232), (233)...IOC belonging to the third group, (3)...Request signal line, (4
)...Acknowledge signal line, (5)...Data line,
(6)...Priority signal line, (7)...Priority signal receiving circuit, (8)...Priority signal transmitting circuit, (9)...FF, αQ...AND gate, 0]) ...Data register, α4. (c)...
・Each group busy line. Note that the symbols in the middle of each figure indicate the same or equivalent parts. Agent Shin Kuzuno - Figure 4 4 Figure 5

Claims (1)

[Claims] In a priority control device that is connected to a central processing unit via a common data line and determines the priority of using the common data line among a plurality of input/output control devices, each of the plurality of input/output control devices is For multiple groups containing at least one input/output control device, the priorities between the groups and the priorities among the input/output control devices within each group are determined in advance, and the group with the lowest priority among the groups is selected. A group busy line is provided for each group and outputs a busy signal when a processing request occurs in at least one input/output control device in the group, and Means for prohibiting access to the common data line after the grouping, and means for prohibiting access from one input/output control device belonging to the same group to that device or an input/output control device with a higher priority in the group pressure than that device. A priority line that outputs a signal to notify lower priority devices in the same group as the device that it is issuing a processing request, and when a signal is present on this priority line, the device in the group A priority control device comprising: means for prohibiting access to the common data line from devices with a low priority.