KR100236330B1 - PCI slave address stepping denice - Google Patents

Abstract

The present invention provides a PCI address stepping device suitable for removing noise that may occur between a plurality of address lines. An interface unit for inputting various signals for performing the operation of the PCI slave from the bus and interfacing to internal signals, and stepping the address input through the PCI bus from the PCI master into a predetermined group according to the control signal output from the interface unit An address stepping decoder unit, a main decoder unit which combines and decodes the decoded addresses divided into predetermined groups in the address stepping decoder unit as a whole, and a control signal which performs a function of a PCI slave by receiving an internal signal output from the interface unit. Exodus The core is configured to include portions which.

Description

PCI Slave Address Stepping Device {PCI slave address stepping denice}

The present invention relates to a PCI (PCI), in particular, when the signal line for transmitting a large amount of signals, such as multi-bit address is turned on at the same time in the PCI master by turning on the address line in several steps in the PCI master It relates to a PCI slave slave address stepping device suitable for carrying an address.

In general, as shown in FIG. 1, a plurality of metal lines 1 for transmitting different signals are formed in a vertical direction in an upper layer and a lower layer.

Typically, a 32-bit address bus consists of 32 metal lines and a 64-bit address bus consists of 64 metal lines (1).

A plurality of devices such as a PCI master, a PCI slave, and a PCI arbiter are connected to the PCI bus.

2 is a block diagram of a master or slave connected to a conventional PCI bus.

Conventionally, the interface unit 23 for inputting various signals input from the PCI master 22 through the PCI bus 21, the decoder unit 24 for decoding the input address, and perform operations as a master and a slave. It is configured to include a core portion 25 for outputting a control signal for.

Here, the interface unit 23, the decoder unit 24, and the core unit 25 are collectively referred to as PCI slave units 26, which receive data and addresses from the PCI master 22.

In such a master or slave, the master may act as a slave and the slave may act as a master.

This depends on which data is sent and on which side the master is active and the slave is passive.

The transmission and reception of data or addresses between these devices is performed under the control of masters according to unique addresses between the devices.

The PCI arbiter of FIG. 2 prevents each master and slave from using the PCI bus 21 at the same time by determining the priority in using the PCI bus 21.

That is, the PCI adapter receives the PCI bus 21 use request signal from each master and slave to adjust the priority.

The conventional PCI address decoding apparatus operates as follows.

As shown in FIG. 2, when a signal for decoding is input from the PCI master 22 connected to the PCI bus to the interface unit 23, the interface unit 23 outputs a control signal to the decoder unit 24.

For example, when an address of 32 bits is input, the decoder unit 24 decodes it and outputs it to the core unit 25.

Accordingly, the core unit 25 performs an operation by outputting a control signal for performing the operation as a master or a slave.

However, in the conventional PCI device, when 32 or 64 address lines are turned on at the same time for data transmission, signals have noise due to interference between respective address lines carrying different signals. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and even though a plurality of address lines are turned on at the same time, a PCI slave suitable for removing noises that may occur between a plurality of signal lines by transmitting signals according to priorities. (Slave) An object of the present invention is to provide an address stepping device.

1 is a perspective view showing a pattern form of a general address line

2 is a configuration diagram of a conventional PCI slave

3 is a configuration diagram of a PCI slave of the present invention

4 is a timing diagram of a PCI slave according to the present invention;

Explanation of symbols for main parts of the drawings

31: PCI master 32: interface

33: address stepping decoder section 34: main decoder section

35 core portion 36 PCI slave

The PCI address stepping device of the present invention for achieving the above object performs the operation of the PCI slave from the PCI bus in transmitting data and address between the PCI master and the PCI slave connected to the PCI bus. An interface unit for inputting various signals for interfacing to internal signals, an address stepping decoder unit for stepping by dividing an address input from a PCI master through a PCI bus according to a control signal output from the interface unit into a predetermined group, and A main decoder unit which combines and decodes the decoded addresses as a whole by the address stepping decoder unit and decodes the whole, and a core unit which receives an internal signal output from the interface unit and outputs a control signal performing a function of a PCI slave. do.

Hereinafter, a PCI address stepping apparatus of the present invention will be described with reference to the accompanying drawings.

3 is a configuration diagram of a PCI address stepping device of the present invention, and FIG. 4 is a signal timing diagram according to the present invention.

First, as illustrated in FIG. 3, the PCI address stepping device of the present invention includes an interface unit 32 for inputting various signals for performing an operation from the PCI master 31 through the PCI bus. Combining the address stepping decoder 33 and the address output from the address stepping decoder 33 into one again by stepping and decoding the addresses input according to the control signal of the interface unit 32 into a predetermined group. And a main decoder unit 34 and a core unit 35 to decode.

Here, the unreferenced PCI adapter receives the use request signal from each master or slave in using the PCI bus and adjusts the priority.

In addition, the interface unit 32, the address stepping decoder unit 33, the main decoder unit 34, and the core unit 35 become one PCI slave 36, and the PCI slave 36 is connected to the PCI master 31. Can perform a function

As described above, the master and the slave perform the same functions and are divided into the master and the slave according to whether data is transmitted or received.

Operation of the PCI address stepping device of the present invention configured as described above is as follows.

First, the PCI address stepping apparatus of the present invention has a function of performing normal decoding and a function of performing decoding by stepping an address.

That is, a function of decoding an address without stepping according to the control signal of the interface unit 32 and a function of stepping and decoding an address according to the control signal of the interface unit 32 may be performed.

This will be described in more detail with reference to the timing diagram of FIG. 4 as follows.

First, when performing the address stepping function, as shown in FIG. 4, before the frame (FRAME) signal of the signal input to the interface unit 32 is input (that is, before the frame signal is changed from high level to low level). When the address is input to the interface unit 32 outputs the chip select signal CS to the address stepping decoder unit 33.

The chip select signal CS becomes active at the low level and steps the address at the rising edge of the clock signal generated during this low level.

At this time, the address stepping is divided into three groups, and as shown in FIG. 4, the address stepping is performed at each rising edge of the clock signal in a section in which the chip select signal is low.

For example, in the case of a 32-bit address, the first group is 0, 3, 6,... The 30th address line is turned on, and the second group has 1, 4, 7,... Turn on the 31st address line.

And the third group is 2, 5, 8,... Turn on the 29th address line.

In this way, if a total of 32 address lines are divided into first, second, and third groups and turned on, noise is not generated between each address line.

Subsequently, after the address of the last group of the three groups is decoded by the address stepping decoder 33, the main decoder 34 decodes the whole and outputs it to the core 35.

Accordingly, the core unit 35 functions as a slave according to an internal signal applied from the interface unit 32.

When performing a general operation without performing the address stepping function, the interface unit 32 does not output the chip select signal to the address stepping decoder 33.

As a result, since the chip select signal continues to have a high level, the address stepping decoder 33 does not operate and the input address is input to the main decoder 34 and decoded as it is.

As described above, the address stepping apparatus of the present invention has the following effects.

In transmitting / receiving a multi-bit address using a PCI bus, an address stepping decoder unit which divides and decodes an address into predetermined groups at the front end of an address decoder of a PCI slave for inputting an address can eliminate noise that may occur between adjacent address lines. have.

Claims (5)

In transferring data and address between PCI master and PCI slave connected to PCI bus, An interface unit for inputting various signals for performing the operation of the PCI slave from the PCI bus and interfacing with internal signals; An address stepping decoder to decode the addresses sent from the PCI master to several groups by a control signal output from the interface unit; A main decoder unit for dividing the decoded addresses into whole groups by decoding the divided into a predetermined group in the address stepping decoder unit; PCI address stepping device comprising a core unit for receiving the internal signal output from the interface unit for outputting a control signal for performing the function of the PCI slave. The method of claim 1, And a control signal output from the interface unit to the address stepping decoder unit is a chip select signal. delete The method of claim 2, And the chip select signal becomes active at a low level. 2. The PCI address stepping apparatus according to claim 1, wherein the address stepping time of the address stepping decoder unit is made at the rising edge of the clock signal.

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