KR19980069052A - PC data and address stepping method - Google Patents

Abstract

In the PCI data and address stepping method of the present invention, the step of determining whether the data or address inputted through the PCI bus is stepped is decoded by the decoder unit when stepping is not necessary, and deciding how many steps to step if necessary. And if the step is determined, detecting whether data and an address are input in accordance with each step; and if the input data and address do not match the set step, determining a stepping error to correct an error and inputting the data. And if the address coincides with the set step, integrating the stepped data and address into one again, and decoding the integrated data and address in the decoder unit.

Description

PC data and address stepping method

The present invention relates to a PCI (PCI) system, and more particularly, to a PCI data and address stepping method suitable for improving data and address stepping speed in a PCI slave receiving data and addresses from a PCI master over a PCI bus.

In general, multiple devices such as a PCI master, a PCI slave, and a PCI arbiter are connected to the PCI bus.

The PCI slave unit receives data and address from the PCI master.

In such a master or slave, the master may act as a slave and the slave may act as a master.

This depends on which data is sent and on which side the master is active and the slave is passive.

The transmission and reception of data or addresses between these devices is performed under the control of masters according to unique addresses between the devices.

The PCI arbiter prioritizes each master and slave in using the PCI bus, preventing it from using the PCI bus at the same time.

That is, the PCI arbiter adjusts priority by receiving PCI bus request signal from each master and slave.

Hereinafter, a conventional PCI address stepping method will be described with reference to the accompanying drawings.

FIG. 1 is a configuration diagram of a conventional PCI address stepping device, and FIG. 2 is a signal timing diagram according to the prior art.

First, as shown in FIG. 1, a conventional PCI address stepping device includes an interface unit 12 for inputting various signals for performing an operation from a PCI master 11 through a PCI bus, and the interface unit. An address stepping decoder 13 for stepping and decoding an address input according to the control signal of (12) into a predetermined group, respectively, and combines and decodes the address output from the address stepping decoder 13 again into one. The main decoder unit 14 and the core unit 15 is configured.

Here, the unreferenced PCI adapter receives the use request signal from each master or slave in using the PCI bus and adjusts the priority.

In addition, the interface unit 12, the address stepping decoder unit 13, the main decoder unit 14, and the core unit 15 become one PCI slave 16, and the PCI slave 16 is connected to the PCI master 11. Can perform a function

As described above, the master and the slave perform the same functions and are divided into the master and the slave according to whether data is transmitted or received.

Referring to the stepping method according to the conventional PCI address stepping device configured as described above are as follows.

First, the conventional PCI address stepping apparatus has a function of performing normal decoding and a function of performing decoding by stepping an address.

That is, a function of decoding an address without stepping according to the control signal of the interface unit 12 and a function of stepping and decoding an address according to the control signal of the interface unit 12 may be performed.

This will be described in more detail with reference to the timing diagram of FIG. 2 as follows.

First, when performing the address stepping function, as shown in FIG. 2, before a frame (FRAME) signal among the signals input to the interface unit 12 is input (that is, before the frame signal is changed from high level to low level). When the address is input to the interface unit 12 outputs the chip select signal CS to the address stepping decoder unit 13.

The chip select signal CS becomes active at the low level and steps the address at the rising edge of the clock signal generated during this low level.

At this time, the address stepping is divided into three groups. As shown in FIG. 2, the address stepping is performed at the rising edge of the clock signal in the section in which the chip select signal is low.

For example, if the address is 32 bits, it is divided into three groups, and the first group is 0, 3, 6,... The 30th address line is turned on, and the second group has 1, 4, 7,... Turn on the 31st address line.

And the third group is 2, 5, 8,... Turn on the 29th address line.

In this way, if a total of 32 address lines are divided into first, second, and third groups and turned on, noise is not generated between each address line.

Subsequently, after the address of the last group of the three groups is decoded by the address stepping decoder unit 13, the main decoder unit 14 decodes the entire group and outputs the decoded group to the core unit 15.

Accordingly, the core unit 15 functions as a slave according to an internal signal applied from the interface unit 12.

In this case, when performing a general operation without performing the address stepping function, the interface unit 12 does not output the chip select signal to the address stepping decoder unit 13.

As a result, since the chip select signal continues to have a high level, the address stepping decoder unit 13 does not operate and the input address is input to the main decoder unit 14 as it is and decoded.

However, the PCI address stepping method as described above has the following problems.

First, the data cannot be stepped but only an address, and furthermore, the speed characteristic is poor because it is stepped in three steps.

Second, it was not possible to check for errors that could occur during stepping.

The present invention has been made to solve the above problems and can be used to step both data and address, and to check for errors that may occur during stepping to improve the reliability of stepping and speed characteristics according to stepping PCI Its purpose is to provide a data and address stepping method.

1 is a block diagram of a conventional PCI address stepping device

2 is a signal timing diagram according to a conventional PCI address stepping device

3 is a flowchart illustrating a PCI data and address stepping method of the present invention.

4 is a signal timing diagram according to the PCI data and address stepping method of the present invention.

Explanation of symbols on the main parts of the drawings

11: PCI master 12: interface

13: PCI address decoding unit 14: decoder unit

15 core part

In the PCI data and address stepping method of the present invention for achieving the above object, it is determined whether or not stepping of the data or address input through the PCI bus is performed by the decoder unit when stepping is not necessary. Determining whether or not to step, and if the step is determined, detecting whether the data and address are input in accordance with each step, and if the input data and address does not match the set step is determined as a stepping error Correcting the error and integrating the stepped data and address into one again if the input data and address match the set steps, and decoding the integrated data and address in the decoder unit.

Hereinafter, the PCI data and address stepping method of the present invention will be described with reference to the accompanying drawings.

3 is a flowchart illustrating a PCI data and address stepping method of the present invention, and FIG. 4 is a signal timing diagram according to the PCI data and address stepping method of the present invention.

First, in the PCI data and address stepping method of the present invention, as shown in FIG. 3, it is determined whether to step through the data and address input through the PCI bus (101). The address is immediately input to the decoder section and decoded 102.

As a result of the determination, if the data and the address need to be stepped, it is determined how many steps (groups) the data and the address are divided (step 103).

At this time, if it is divided into three steps, the input data and address are divided into three steps (104). If it is divided into four steps, it is detected whether the input address is divided into four steps. (105)

It is determined whether an error signal is generated according to the respective detection results (106). If an error signal is generated, error correction is performed.

If the error signal is not generated, it recognizes that the input data and address are correctly stepped according to the set step and integrates the data and address into the data and address before stepping (108).

The integrated data and address are then input to the decoder section and decoded (109).

4 illustrates a signal timing diagram according to the PCI data and address stepping method.

4A illustrates a clock signal, b of FIG. 4 represents a reset signal, and c of FIG. 4 represents an active state at a low level as the chip select signal CS.

As shown in c of FIG. 4, when the chip select signal is switched from the high level to the low level, data or an address is stepped and input.

Here, the stepping level is set to 4 steps, and it is shown that an address divided into 4 steps is input in a section in which the chip select signal is at a low level.

When the chip select signal is switched to the high level and then to the low level again, data divided into three steps is input this time.

Subsequently, as shown in FIG. 4E, when the address of the last fourth group of the addresses divided and input into the four steps is input, the addresses divided into the four steps (groups) are merged into one again.

Subsequently, as shown in f of FIG. 4, when an integrated address is input, a finish signal indicating that the input of the address is finished is input.

One of the important features of the present invention is an error signal as shown in Fig. 4G, when the input data and address are set to the first stepping level, i.e., 3 steps or 4 steps. Is detected if it is input and not generated.

As described above, the PCI data and address stepping method of the present invention has the following effects.

First, data and address can be stepped, which improves the speed of data and address transfer between master and slave in PCI systems.

Second, it is possible to check for errors that occur during stepping, which improves the reliability of system operation.

Third, other functions such as an initialization function can be performed simultaneously while decoding data and addresses.

Claims (2)

Determining whether the data or address inputted through the PCI bus is stepping, and if the stepping is not necessary, decoded by the decoder unit and deciding how many steps to step if necessary. If the step is determined, detecting whether data and an address are input in accordance with each step; If the input data and address do not coincide with the set step, determine a stepping error, correct the error, and if the input data and address coincide with the set step, consolidate the stepped data and address into one again; PCI data and address stepping method comprising the step of decoding the integrated data and address in the decoder unit. The method of claim 1, And said step is set to 3 steps or 4 steps and more.