JPS592379B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and particularly to a semiconductor memory with a high degree of integration and a high read/write speed.

It is well known that when a semiconductor and a different substance or semiconductors with different properties come into contact with each other, a contact potential difference is generated between the two, which acts as a potential barrier against holes or conduction electrons.

When a region substantially surrounded by a potential barrier is formed in a semiconductor, this region has the function of storing charge.

If two such cells are brought into contact via a potential barrier and the potential relationship between the two cells or the height of the potential barrier between the two cells is controlled, charges can be exchanged between the two cells and the cell can function as a memory. be able to. The inventor of the present application has already proposed that in this type of memory, a region to form a potential barrier is formed of a region of the same conductivity type as the moving charges, a region of the opposite conductivity type, or an intrinsic region, and the effective height of the potential barrier is two cells. proposed a semiconductor memory that could be controlled by the potential between
.

When the potential barrier is provided by a region of opposite conductivity type, various parameters are selected such that this region of opposite conductivity type only punches through between two cells. Therefore, in either case, the charge travels mostly due to the drift caused by the electric field.
In addition, two cells are arranged in a direction substantially perpendicular to the surface to allow charge to move by bulk mobility, increasing operating speed and surface utilization. An example of its structure is shown in FIG. Figure 1a is a plan view, and Figure 1b is A-A' in Figure 1a.
It is a sectional view along a line. π regions 13 are provided in a matrix in the p* region 14, the vertical dotted lines indicate the n'' buried layer 12, and the horizontal dashed-dotted lines indicate the word lines 1 provided on the surface. , one of the n- or p-regions provided in a matrix in the pf region 14 corresponds to one memory cell.
The n region 13 almost completely becomes a depletion layer due to the diffusion potential of the pfn' junction. The bit line n* region 2 is a buried layer provided vertically in the figure. When a write voltage of about 10V is applied to the word line, bit line 1
Electrons are injected from 2 and accumulated near the surface.
In the store state (state 1 is stored), the potential of the word line is set to about half the write voltage. For memory cells to which it is not desired to write data (or to which state 0 is to be written), the potential of the bit line may be made as high as that of the word line. Data can be read by lowering the word line potential to about the set potential. The stored electrons flow into the bit line. Since electrons flow not only by diffusion but also by drift due to the diffusion potential of the p+n junction, the readout speed is fast. During writing, a strong electric field is generated across the potential barrier in front of the bit line, so the writing speed is extremely fast. Furthermore, since it uses the properties of a semiconductor bulk, the write and read speeds are faster than previous memory cells that use surface conduction. The impurity density of the p region 104 and the spacing between the bit lines 12 may be selected so that the gap between the bit lines becomes a depletion layer, leaving a small neutral region, so that no exchange of electrons occurs. The structure shown in FIG. 1 can easily increase the speed as described above. However, the width Wc of the n-region 13 surrounded by the gate p+ region 14
Since the thickness of the gate p+ region 14 is often made to be less than twice the thickness of the depletion layer that expands at 0 bias, it increases approximately in proportion to the reciprocal of the square root of the impurity density of the n- region 13, reducing the integration density. Put it away. The present invention provides a semiconductor memory that has improved the above-mentioned drawbacks, and enables it to have a high degree of integration without significantly impairing the conventional low capacitance.

The gist of the present invention is to provide a step-like or gentle impurity density distribution in a low impurity density region where a gate is formed,
The impurity density on the main surface side where the gate is formed is made relatively high to narrow the gate spacing, and a layer with lower impurity density or an intrinsic semiconductor layer is formed under the gate to reduce the capacitance around the gate. It is something that decreases. The present invention will be explained in detail below using the drawings.

FIG. 2 is an example of the present invention, and shows an example of a cross-sectional structure when memory cells are arranged two-dimensionally.

M between the n+ region 12 embedded in the p-type substrate 104 and the surface
Electrodes 1 having an IS structure form an X-Y matrix. Writing, storage, and reading are performed by voltage control of each electrode 1, 12, and possibly 4 (or p-type region 14). Since the diffusion potential can be increased due to the presence of the low impurity density region 13' having a relatively high impurity density, leakage during accumulation can be reduced, and the capacitance can be reduced due to the presence of the lower impurity density (or intrinsic semiconductor) region 113. Therefore, high-speed writing and reading becomes possible.
Furthermore, it is most effective if the degree of integration of the storage device can be improved. The structure of the gate region is a shot key structure, M
IS structures can be used and are not limited to the structure shown in FIG. Furthermore, it is of course possible to form a nonvolatile memory by providing a floating gate. Low impurity density region 1 with relatively high impurity density
3' has an impurity density of 1017c7rL-3 or less, and the thickness is appropriately selected depending on the purpose.

The impurity density of the lower impurity density region 113 is 1
Channel width WC, preferably 015cTrL-3 or less
Thickness of l-gate p+ region 14 and n-region 13', n-
(or i) The impurity density and thickness of the region 113 are selected appropriately depending on the purpose, but for example, in a normally-off type in which the state where no voltage is applied to the gate 4 (0 bias or open) is used as the off state, the diffusion potential of the gate junction As a potential barrier is formed in the channel, in other words, as if a depletion layer binds the channel region, the n layer 13'
It is desirable to select the impurity density and channel width Wc of , and it is even more desirable that the n' (or 1) layer 113 is also completely depleted in order to reduce the minority carrier accumulation effect. In the normally-on type, on the contrary, it is desirable that charge-neutral approximation regions are formed in the channel, and the impurity density and dimensions of each region are selected. According to the invention, n
Due to the presence of the layer 13', the channel width Wc can be narrowed, and the integration density can be improved when integrated circuits are formed. Although several specific examples have been described above, it is also possible to reverse the conductivity type of each region.

Furthermore, although Si was taken as an example of a semiconductor material, Ge, G
A, As, etc., intergroup compounds and their mixed crystals can be used, and since the operating voltage is low, it does not necessarily have to be a single crystal, and a polycrystalline or amorphous semiconductor may form a part or the whole. . Manufacturing methods include well-known crystal growth technology, impurity diffusion, alloying, impurity addition technology such as ion implantation,
A selective punching technique or the like can be used. The semiconductor memory device according to the present invention has low power consumption, can perform high-speed writing and reading, and can be highly integrated.
There are countless applications such as RWM, ROM, nonvolatile memory, etc., and the industrial value is extremely high.

[Brief explanation of drawings]

1A and 1B are a conventional semiconductor memory proposed by the inventor of the present application, in which a is a plan view, b is a cross-sectional view along AOA-A',
FIG. 2 shows an example of application of the present invention.

Claims (1)

[Claims] 1 A semiconductor chip is used, and a memory matrix including a plurality of word lines and a plurality of bit lines includes memory cells at at least some of the intersections thereof, and the memory cells are of a first conductivity type formed in the semiconductor chip. a semiconductor bit region having a high impurity density, a semiconductor accumulation region formed on the surface portion of the semiconductor chip, and at least two or more semiconductor bit regions having different impurity densities formed between the semiconductor bit region and the semiconductor accumulation region. a high-resistance semiconductor region formed on the semiconductor chip in proximity to the semiconductor accumulation region;
A high-resistance semiconductor region having an insulated electrode structure for controlling the potential of the semiconductor storage region and a gate region provided adjacent to the two or more high-resistance semiconductor regions, the gate regions having the narrowest interval. 1. A semiconductor memory characterized in that the impurity density of the semiconductor region is higher than the impurity density of other high-resistance semiconductor regions.