JPS60194573A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS60194573A
JPS60194573A JP5061884A JP5061884A JPS60194573A JP S60194573 A JPS60194573 A JP S60194573A JP 5061884 A JP5061884 A JP 5061884A JP 5061884 A JP5061884 A JP 5061884A JP S60194573 A JPS60194573 A JP S60194573A
Authority
JP
Japan
Prior art keywords
formed
groove
whole surface
over
surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5061884A
Inventor
Tetsuya Iizuka
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5061884A priority Critical patent/JPS60194573A/en
Publication of JPS60194573A publication Critical patent/JPS60194573A/en
Application status is Granted legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation

Abstract

PURPOSE:To obtain the titled device of high density necessitating no wide areas by a method wherein charges are given and received between the first and second gate electrodes by making Cd larger than Cu, and memory transistors are formed in a groove and around it. CONSTITUTION:The first thin gate oxide film 15 is formed on the inner wall of the groove 13 and on the surface of a substrate 11 by thermal oxidation, and a polycrystalline Si film is buried in the groove 13 by being deposited over the whole surface; thereafter, the unnecessary parts are etched, thus forming a floating gate 16 buried in the groove 16 via first gate oxide film 15. Next, the second thin gate oxide film 17 is formed on the surface of the floating gate 16 by thermal oxidation. After deposition of a polycrystalline Si film over the whole surface, a control gate 18 is formed by patterning. After successive deposition of an interlayer insulation film 19 over the whole surface, a contact hole not illustrated is bored; further, a wiring metal is evaporated over the whole surface. Thereafter, a wiring not illustrated is formed by patterning and thus the EEPROM cell is produced.
JP5061884A 1984-03-16 1984-03-16 Semiconductor memory device Granted JPS60194573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5061884A JPS60194573A (en) 1984-03-16 1984-03-16 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5061884A JPS60194573A (en) 1984-03-16 1984-03-16 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS60194573A true JPS60194573A (en) 1985-10-03

Family

ID=12863960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5061884A Granted JPS60194573A (en) 1984-03-16 1984-03-16 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS60194573A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774556A (en) * 1985-07-25 1988-09-27 Nippondenso Co., Ltd. Non-volatile semiconductor memory device
JPH0344970A (en) * 1989-07-13 1991-02-26 Toshiba Corp Cell structure for semiconductor storage device
JPH03233974A (en) * 1990-02-08 1991-10-17 Matsushita Electron Corp Manufacture of nonvolatile semiconductor memory
DE19525756A1 (en) * 1994-07-14 1996-02-08 Micron Technology Inc Field isolation device floating control terminal and method for manufacturing the device
JP2008141195A (en) * 2006-11-30 2008-06-19 Dongbu Hitek Co Ltd Semiconductor device and method of manufacturing the same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4774556A (en) * 1985-07-25 1988-09-27 Nippondenso Co., Ltd. Non-volatile semiconductor memory device
JPH0344970A (en) * 1989-07-13 1991-02-26 Toshiba Corp Cell structure for semiconductor storage device
JPH03233974A (en) * 1990-02-08 1991-10-17 Matsushita Electron Corp Manufacture of nonvolatile semiconductor memory
DE19525756A1 (en) * 1994-07-14 1996-02-08 Micron Technology Inc Field isolation device floating control terminal and method for manufacturing the device
US5693971A (en) * 1994-07-14 1997-12-02 Micron Technology, Inc. Combined trench and field isolation structure for semiconductor devices
US5903026A (en) * 1994-07-14 1999-05-11 Micron Technology, Inc. Isolation structure for semiconductor devices
US6130140A (en) * 1994-07-14 2000-10-10 Micron Technology, Inc. Method of forming an isolation structure in a semiconductor device
US6479880B1 (en) 1994-07-14 2002-11-12 Micron Technology, Inc. Floating gate isolation device
DE19525756B4 (en) * 1994-07-14 2005-06-30 Micron Technology, Inc. Isolation structure for semiconductor devices floating control terminal and processes for their preparation
JP2008141195A (en) * 2006-11-30 2008-06-19 Dongbu Hitek Co Ltd Semiconductor device and method of manufacturing the same

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