JPH0559585B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a bipolar transistor memory with a punch-through base that has a high degree of integration and a fast read/write speed.

[Technology background]

When a region substantially surrounded by a potential barrier is formed in a semiconductor, this region has the function of storing charge. If such cells are brought into contact via two potential barriers and the potential relationship between the two cells or the height of the potential barrier between them is controlled, the charge can be reduced by 2.
It can communicate between two cells and can function as memory.

The inventor of the present application has already proposed that in this type of memory, a region to form a potential barrier is formed of a region of the same conductivity type as the moving charges, a region of the opposite conductivity type, or an intrinsic region, and the effective height of the potential barrier is two cells. proposed a semiconductor memory that could be controlled by the potential between
−58982 (Special Application No. 18465), Special Publication No. 1846-
No. 52348 (Patent Application No. 52-20653)). When the potential barrier is provided by a region of opposite conductivity type, various parameters are selected such that this region of opposite conductivity type only punches through between two cells. Therefore, in either case, the charge travels mostly due to the drift caused by the electric field. In addition, two cells are arranged in a direction substantially perpendicular to the surface to allow charge to move by bulk mobility, increasing operating speed and surface utilization. An example of its structure is shown in FIG. FIG. 1a is a plan view, and FIG. 1b is a sectional view taken along line A-A' in FIG. 1a. n ^- in matrix form in p ⁺ area 14
A region 13 is provided, in which the vertical dotted line indicates the n ⁺ buried layer 12 and the horizontal dashed-dotted line indicates the word line 1 provided on the surface. In these figures, the p ⁺ region 14 has a
One of the n ^- or p ^- regions each corresponds to one memory cell. In FIG. 1b, the n-region 13 is almost completely depleted at the diffusion potential of the p ⁺ n ^- junction.
The bit line n ⁺ region 12 is a buried layer provided vertically in the figure. When a write voltage of, for example, about 10 V is applied to the word line, electrons are injected from the bit line 12 and accumulated near the surface. In the store state (state 1 is stored), the potential of the word line is set to about half the write voltage. For memory cells to which it is not desired to write data (or to which state 0 is to be written), the potential of the bit line may be made as high as that of the word line. Data can be read by lowering the word line potential to about the ground potential. The stored electrons flow into the bit line. The readout speed is fast because electrons flow not only by diffusion but also by drift due to the diffusion potential of the p ⁺ n ^-junction . During writing, a strong electric field is applied beyond the potential barrier in front of the bit line, so
Writing speed is very fast. Furthermore, since it uses the properties of a semiconductor bulk, the write and read speeds are faster than previous memory cells that use surface conduction. The impurity density of the p region 104 and the spacing between the bit lines 12 may be selected so that the space between the bit lines 12 becomes almost a depletion layer, leaving a small neutral region, so that no exchange of electrons occurs.

[Problems with conventional technology]

The structure shown in FIG. 1 can easily increase the speed as described above. However, the width W _c of ^{the n - region} 13 surrounded by the gate p ⁺ region 14 is
Since the thickness is often set to less than twice the thickness of the depletion layer that expands at 0 bias from 0 to 0, the thickness increases approximately in proportion to the reciprocal of the square root of the impurity density of the n ^- region 13, and the integration density decreases.

[Purpose of the invention]

The present invention provides a semiconductor memory that has improved the above-mentioned drawbacks, and enables it to have a high degree of integration without significantly impairing the conventional low capacitance.

[Summary of the invention]

The present invention is based on the original application (Patent No. 1225198 (Japanese Unexamined Patent Publication No. 53-116084, Japanese Patent Publication No. 59-2379))
This is a divisional application. In the original application, the right was claimed for the SIT structure in which the bit line region and the channel region are of the same conductivity type, but in the present invention, the base region of the opposite conductivity type to the bit line region exists in the channel region. We propose a bipolar transistor structure.

The gist of the present invention is to provide a step-like or gentle impurity density distribution in a low impurity density region where a base electrode extraction region (gate region) is formed;
The impurity density on the main surface side where the base electrode extraction region (gate region) is formed is made relatively high, and the interval between the base electrode extraction regions (gate region) is narrowed. In this method, a layer with a lower impurity density or an intrinsic semiconductor layer is formed to reduce the capacitance around the base electrode extraction region (gate region).
A p-substrate, a plurality of bit lines formed by an n ⁺ buried layer on top of the p-substrate, an ^n- first channel region above the bit lines, and an n- first channel region above the bit ^lines .
a plurality of mutually independent second channel regions, a p ⁺ base electrode extraction region formed to sandwich each of the second channel regions, and a p + base electrode connected to the p ⁺ base electrode with only punch-through.
The channel includes a base region and a plurality of word lines formed to form a capacitor for charge storage through an insulator on the upper part of the second channel region, and includes a plurality of bit lines and a plurality of word lines. A memory cell of a bipolar transistor whose base is punch-through is formed in a few common parts of the memory matrix formed by the memory matrix.

[Embodiments of the invention]

The present invention will be explained in detail below using the drawings.

FIG. 2 is an example of the present invention, and shows an example of a cross-sectional structure when memory cells are arranged two-dimensionally. N ⁺ region (bit line) embedded in p-type substrate 104
12 and an electrode with MIS structure on the surface (word line)
1 form an XY matrix. The impurity density and thickness of base p region 114 are selected so that there is only punch-through in the main operating region. The emitter and collector regions of the bipolar transistor constituting the unit cell are the upper part of the low impurity density region 133 and the n ⁺ region 12, and are interchangeable. In FIG. 2a, an n-type low impurity density region in which a channel is formed is sandwiched between a p base region 114 and a second channel region 133 having a relatively high impurity density and a second channel region 133 having a relatively high impurity density (or an intrinsic semiconductor). It consists of one channel area 113. In FIG. 2b, the p base region 114 is formed inside the second channel region 133 of n type and high impurity density, and the first channel region 113 of n type and low impurity density is formed thereunder. There is. this
Since BPT only has a punch-through base, the potential barrier at the base is controlled by electrostatic induction, and has similar advantages to SIT, but operates in a normally-off type. It has almost the same operating mechanism as SIT, but unlike SIT, the impurity density of the p base region 114 is selected regardless of the impurity density of the n ^- layer 133, so that the base electrode can be taken out.
Since the interval W _c between the p ⁺ regions 141 can be narrowed, high integration density is possible. Figure 2 a is
FIG. ^{2b shows a case where the base electrode extraction p + area} 141 is formed on the surface, and FIG. It is formed on the insulator 20 formed in the above. Second
In FIG. 2B, a punch-through base p region 114 is formed inside the second channel region 133, and in FIG.
A punch-through base p region 114 is formed at the boundary between the second channel region 133 and the second channel region 133 . 2a and 2b are cross-sectional views taken in directions orthogonal to each other, and although only one bit line 12 is shown in FIG. It is clear that there will be a plurality of lines 12. Writing, storage, and reading are carried out on each electrode 1, 12, possibly 4 (or p-type region 1).
41) by voltage control. Since the diffusion potential can be increased due to the presence of the low impurity density region 133 with a relatively high impurity density, leakage during accumulation can be reduced, and the capacitance can be reduced due to the presence of the low impurity density (or intrinsic semiconductor) region 113. , high-speed writing and reading become possible. Furthermore, it is most effective if the degree of integration of the storage device can be improved.

The low impurity density region 133 having a relatively high impurity density has an impurity density of 10 ¹⁷ cm ^-3 or less, and the thickness is appropriately selected depending on the purpose. The impurity density of the lower impurity density region 113 is 10 ¹⁵ cm
^-3 or less is desirable. Channel width W _c , base p ⁺
The thickness of the region 141 and the impurity density of the n ^- region 133, the n ^- (or i) region 113, and the base p
The impurity density and thickness of the region 114 are appropriately selected depending on the purpose, ^but the impurity density and p
It is desirable to select the impurity density and channel width W _c of the region 114, and also ^to
It is further desirable that all of the carriers be depleted in order to reduce the minority carrier accumulation effect.

〔Effect of the invention〕

According to the present invention, due to the presence of the p base region 114, the channel width W _c can be narrowed, and the integration density can be improved when integrated circuits are formed.

According to the present invention, since the n ^- layer 113 can be made to have a low impurity density and the n ^- layer 133 can be made to have a high impurity density, the junction capacitance of the base and the base electrode extraction region can be made small, so that high-speed writing and reading can be achieved. I can do it. According to the invention n ^-layer 1
The impurity density of 33 can be increased, and the p base layer 114
Since the diffusion potential can be increased, leakage during storage can be reduced, and memory retention time can be extended.

Although several specific examples have been described above, it is also possible to reverse the conductivity type of each region. Furthermore, although Si is taken as an example as a semiconductor material, intergroup compounds such as Ge and GaAs and their mixed crystals can also be used, and their operating voltages are low, so they do not necessarily have to be single crystals, but polycrystals, polycrystals, etc. Part or all of the amorphous semiconductor may be formed. As for the manufacturing method, well-known crystal growth techniques, impurity diffusion, alloying, impurity addition techniques such as ion implantation, selective etching techniques, etc. can be used.

The semiconductor memory device according to the present invention has low power consumption, high-speed writing and reading, and can be highly integrated, so it has countless applications such as RAM, RWM, POM, and non-volatile memory.
Its industrial value is extremely high.

[Brief explanation of the drawing]

1A and 1B are a conventional semiconductor memory proposed by the inventor of the present invention, in which a is a plan view, b is a sectional view taken along line A-A', and FIG. 2 is an application example of the present invention. 1... Word line, 4... Base electrode, 12...
Bit line, 20, 21... Insulator, 113... First channel region, 114... Base region, 1
31...Second channel region, 141...Base electrode extraction region, 104...Substrate.

Claims (1)

[Claims] 1 A semiconductor substrate 104 of a first conductivity type, a plurality of bit lines 12 of a second conductivity type with high impurity density and of a conductivity type opposite to the first conductivity type formed on the upper part of the semiconductor substrate, and the bit lines 104 of a first conductivity type. the second formed on the top of
Conductive type low impurity density first channel region 11
3, a plurality of mutually independent second channel regions 133 of a second conductivity type formed above the first channel region and having a higher impurity density than the first channel region; A first conductivity type high impurity density base electrode extraction region 141 is formed to sandwich each of the plurality of second channel regions, and a base electrode extraction region 141 is formed adjacent to the base electrode extraction region and the second channel region. a base region 114 of the first conductivity type, and an insulator 2 formed on the top of the second channel region.
1 and a plurality of word lines 1 formed on top of the insulator, the base region includes the first channel region existing on the base region and a plurality of word lines 1 formed on the insulator. A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit is about to punch through due to a diffusion potential with the first channel region or the second channel region existing below.