JPS5923430Y2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5923430Y2 JPS5923430Y2 JP1349879U JP1349879U JPS5923430Y2 JP S5923430 Y2 JPS5923430 Y2 JP S5923430Y2 JP 1349879 U JP1349879 U JP 1349879U JP 1349879 U JP1349879 U JP 1349879U JP S5923430 Y2 JPS5923430 Y2 JP S5923430Y2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- punching
- film layer
- electrode
- around
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置に関し、特に能率よく自動的にマウ
ントとポンチ゛イングを行なえるようにした半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device that can be mounted and punched efficiently and automatically.
半導体素子は品種により、種々の大きさと電極形状を有
している。Semiconductor elements have various sizes and electrode shapes depending on the type.
これらの半導体素子は同一のダイマウント装置およびポ
ンチ゛イング装置により組立てる場合には、上述のよう
に半導体素子の大きさと電極形状の違いにより半導体素
子内のポンチ゛イング位置が品種によって変わる。When these semiconductor devices are assembled using the same die mount device and punching device, the punching position within the semiconductor device changes depending on the type of semiconductor device due to the difference in the size of the semiconductor device and the shape of the electrodes, as described above.
このため、ポンチ゛イング作業者は個々の半導体素子を
ボンディング線と電極のボンディング部とを位置合せし
てポンチ゛イング作業をしていたので、作業性が非常に
悪かった。For this reason, the punching operator had to perform the punching operation by aligning the bonding wires and the bonding portions of the electrodes of the individual semiconductor elements, resulting in very poor work efficiency.
このためマウントとポンチ゛イングの自動化が進められ
て、その一方法として、ＴＶカメラを用いて光学的にポ
ンチ゛イング部を認識して、位置合せするやり方がある
。For this reason, automation of mounting and punching is progressing, and one method is to optically recognize and align the punching part using a TV camera.
この方法は半導体素子のポンチ゛イング部の金属層と電
極部以外の絶縁膜層との光の反射の強弱によりボンディ
ング部を認識する。In this method, the bonding portion is recognized by the intensity of light reflection between the metal layer of the punching portion of the semiconductor element and the insulating film layer other than the electrode portion.
この場合、ボンディング部周辺の絶縁膜層の幅が狭いと
ポンチ゛イング部とその近傍の電極部とが光学的につな
がってポンチ゛イング位置決めが不正確となり、ボンデ
ィング線がポンチ゛イング部よりずれて電極間ショート
等の不具合が生じやすいという欠点を有していた。In this case, if the width of the insulating film layer around the bonding part is narrow, the punching part and the electrode part in the vicinity will be optically connected, resulting in inaccurate punching positioning, and the bonding line will shift from the punching part, resulting in short circuits between the electrodes. It had the disadvantage that problems were likely to occur.
本考案の目的は光学的に認識しやすい電極形状にして上
記従来の欠点を除去するようにした半導体装置を提供す
ることにある。An object of the present invention is to provide a semiconductor device that has an electrode shape that is easy to optically recognize and eliminates the above-mentioned conventional drawbacks.
本考案は任意形状の電極のポンチ゛イング部において、
ポンチ゛イング部周辺の露出された絶縁膜層をボンディ
ング部周辺以外の部分に比べて幅広く設けたことを特徴
とする半導体装置を提供することにある。In the punching part of an electrode of arbitrary shape, the present invention
It is an object of the present invention to provide a semiconductor device characterized in that an exposed insulating film layer around a punching part is wider than a part other than around a bonding part.
次に本考案について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.
第１図は一実施例の平面図、第２図は第１図のＡ−Ａ′
線断面図を示す。Figure 1 is a plan view of one embodiment, Figure 2 is A-A' in Figure 1.
A line cross-sectional view is shown.
これらの第１図および第２図において、半導体素子１に
はコレクタ領域２、ベース、領域３、およびエミッタ領
域４が形成されている。1 and 2, a semiconductor element 1 has a collector region 2, a base region 3, and an emitter region 4 formed therein.
このようなベース領域３はベース電極５をまたエミッタ
領域４はエミッタ電極６をそれぞれ有していて、７は絶
縁膜を示す。The base region 3 has a base electrode 5, the emitter region 4 has an emitter electrode 6, and 7 indicates an insulating film.
このような半導体素子１のベース電極５またはエミッタ
電極６のそれぞれのボンディング部８，９周辺に露出さ
れた絶縁膜層１０が形成され、かつ、この絶縁膜層１０
の幅はポンチ゛イング部周辺以外の絶縁膜層のそれぞれ
と比べて広くなる。An exposed insulating film layer 10 is formed around the respective bonding parts 8 and 9 of the base electrode 5 or emitter electrode 6 of the semiconductor element 1, and this insulating film layer 10
The width of the insulating film layer is wider than that of each of the insulating film layers except around the punching part.
上記構成の本考案による一実施例に示す半導体装置にお
いてはベース電極５またはエミッタ電極６のそれぞれの
ポンチ゛イング部８，９の周辺の露出された絶縁膜層１
０をボンディング部８，９周辺以外の部分に比べて幅広
く設けることにより、ポンチ゛イング部とその近傍の電
極部とを光学的につながるのを防ぐことか゛できる。In the semiconductor device shown in one embodiment of the present invention having the above structure, the exposed insulating film layer 1 around the respective punching portions 8 and 9 of the base electrode 5 or the emitter electrode 6 is
By providing 0 wider than the portions other than the periphery of the bonding portions 8 and 9, it is possible to prevent the punching portion from being optically connected to the electrode portion in the vicinity thereof.
本考案は以上説明したように、任意電極形状において、
ポンチ゛イング部周辺の露出された絶縁膜層の幅をボン
ディング部周辺以外の部分に比べて広く設けることによ
り、ポンチ゛イング部は光学的に認識しやすくなり、自
動的に位置合せを行なうことができるので、ダイマウン
ト作業とボンディング作業の能率向上の効果を有する。As explained above, in the present invention, in an arbitrary electrode shape,
By making the width of the exposed insulating film layer around the punching part wider than the area other than around the bonding part, the punching part becomes easier to optically recognize and alignment can be performed automatically. It has the effect of improving the efficiency of die mounting work and bonding work.
図面は本考案による半導体装置を示し、第１図は実施例
の概略構成を示す平面図、第２図は第１図のＡ−Ａ’線
断面図である。
１・・・・・・半導体素子、２・・・・・・コレクタ領
域、３・・・・・・ベース領域、４・・・・・・エミッ
タ領域、５・・・・・・ベース電極、６・・・・・・エ
ミッタ電極、７・・・・・・絶縁膜層、８・・・・・・
ベースポンチ゛イング部、９・・・・・・エミッタポン
チ゛イング、１０・・・・・・幅広な絶縁膜層。The drawings show a semiconductor device according to the present invention, and FIG. 1 is a plan view showing a schematic configuration of an embodiment, and FIG. 2 is a sectional view taken along the line AA' in FIG. 1. DESCRIPTION OF SYMBOLS 1...Semiconductor element, 2...Collector region, 3...Base region, 4...Emitter region, 5...Base electrode, 6...Emitter electrode, 7...Insulating film layer, 8...
Base punching part, 9...Emitter punching, 10...Wide insulating film layer.
Claims (1)
に光に反射しにくい絶縁膜層を設け、かつ、その幅をボ
ンディング部周辺以外の絶縁膜層の幅よりも広くしたこ
とを特徴とする半導体装置。A semiconductor characterized in that an insulating film layer that is difficult to reflect light is provided around a bonding part of an electrode having an arbitrary shape that easily reflects light, and the width of the insulating film layer is wider than the width of the insulating film layer other than around the bonding part. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1349879U JPS5923430Y2 (en) | 1979-02-05 | 1979-02-05 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1349879U JPS5923430Y2 (en) | 1979-02-05 | 1979-02-05 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55115051U JPS55115051U (en) | 1980-08-13 |
| JPS5923430Y2 true JPS5923430Y2 (en) | 1984-07-12 |
Family
ID=28831699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1349879U Expired JPS5923430Y2 (en) | 1979-02-05 | 1979-02-05 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5923430Y2 (en) |
-
1979
- 1979-02-05 JP JP1349879U patent/JPS5923430Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55115051U (en) | 1980-08-13 |
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