JP2001339028A - Connector type semiconductor element - Google Patents
Connector type semiconductor elementInfo
- Publication number
- JP2001339028A JP2001339028A JP2000156708A JP2000156708A JP2001339028A JP 2001339028 A JP2001339028 A JP 2001339028A JP 2000156708 A JP2000156708 A JP 2000156708A JP 2000156708 A JP2000156708 A JP 2000156708A JP 2001339028 A JP2001339028 A JP 2001339028A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- connector
- semiconductor chip
- type semiconductor
- solder layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4007—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/40247—Connecting the strap to a bond pad of the item
- H01L2224/40249—Connecting the strap to a bond pad of the item the bond pad protruding from the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8434—Bonding interfaces of the connector
- H01L2224/84345—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/84385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はコネクター型半導体
素子に関し、特に半導体チップと接合するコネクターの
搭載精度に改良を施したコネクター型半導体素子に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connector-type semiconductor device, and more particularly to a connector-type semiconductor device having improved mounting accuracy of a connector to be joined to a semiconductor chip.
【０００２】[0002]
【従来の技術】従来、例えば整流素子として用いられる
コネクター型半導体素子としては、図４（Ａ）〜（Ｄ）
に示す構造のものが知られている。ここで、図４（Ａ）
は同半導体素子の平面図、図４（Ｂ）は図４（Ａ）のＹ
矢視図、図４（Ｃ）は図４（Ａ）のＸ−Ｘ線に沿う断面
図、図４（Ｄ）は同半導体素子の一構成である第２のリ
ードの平面図を示す。2. Description of the Related Art Conventionally, as a connector type semiconductor element used as, for example, a rectifying element, FIGS.
The structure shown in FIG. Here, FIG.
FIG. 4B is a plan view of the semiconductor device, and FIG.
4C is a cross-sectional view taken along line XX of FIG. 4A, and FIG. 4D is a plan view of a second lead which is one configuration of the semiconductor element.
【０００３】図中の付番１は、第１のリードを示す。こ
の第１のリード１と離間した位置には、一部が高さ方向
に第１のリード１と段違いに配置された第２のリード２
が配置されている。ここで、第２のリード２は、図４
（Ｄ）に示すように平面形状が略「Ｈ」の形をなしてい
る。前記第１のリード上１上には、第１の半田層３を介
して半導体チップ４が搭載されている。[0003] Reference numeral 1 in the drawing indicates a first lead. At a position separated from the first lead 1, a second lead 2, a part of which is arranged differently from the first lead 1 in the height direction, is provided.
Is arranged. Here, the second lead 2 corresponds to FIG.
As shown in (D), the planar shape is substantially “H”. A semiconductor chip 4 is mounted on the first lead 1 via a first solder layer 3.
【０００４】前記半導体チップ４，第２のリード２上に
は、第２の半田層５，第３の半田層６を夫々介してコネ
クター７が接合されている。ここで、コネクター７の端
部（図４（Ａ），（Ｃ）の右端部）には、前記第２のリ
ード２の切欠部２ａに装着して係止するコネクター爪８
を有している。また、前記半導体チップ４との接合面の
一部に相当する前記コネクター７の一部は、エンボス加
工により突起９が形成されている。前記半導体チップ
４、コネクター７、第１のリード１の一部、及び第２の
リード２の一部は、樹脂製の外囲器１０により封止され
ている。A connector 7 is joined to the semiconductor chip 4 and the second lead 2 via a second solder layer 5 and a third solder layer 6, respectively. Here, at the end of the connector 7 (the right end in FIGS. 4A and 4C), a connector claw 8 to be fitted and locked in the cutout 2a of the second lead 2 is provided.
have. Further, a part of the connector 7 corresponding to a part of a bonding surface with the semiconductor chip 4 has a projection 9 formed by embossing. The semiconductor chip 4, the connector 7, a part of the first lead 1, and a part of the second lead 2 are sealed by a resin envelope 10.
【０００５】ところで、こうした構成の半導体素子は次
のようにして製作する。まず、第１のリード１上に第１
の半田層３を、第２のリード２上に第３の半田層６を夫
々同時に形成する。つづいて、第１のリード１上に第１
の半田層３を介して半導体チップ４を搭載する。次に、
半導体チップ４、前記第２のリード２上に第２の半田層
５，第３の半田層６を夫々介してコネクター７を載せ
る。このとき、コネクター爪８を第２のリード２の切欠
部２ａに食い込む。ひきつづき、リフローを施し、各半
田層３，５，６を融着させた後、モールドを行い外囲器
１０を形成する。A semiconductor device having such a structure is manufactured as follows. First, the first lead 1 is placed on the first lead 1.
And the third solder layer 6 is simultaneously formed on the second lead 2 respectively. Subsequently, the first lead 1
The semiconductor chip 4 is mounted via the solder layer 3 of FIG. next,
A connector 7 is mounted on the semiconductor chip 4 and the second lead 2 with a second solder layer 5 and a third solder layer 6 interposed therebetween. At this time, the connector claw 8 bites into the notch 2a of the second lead 2. Subsequently, reflow is performed, and after the solder layers 3, 5, and 6 are fused, molding is performed to form the envelope 10.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
半導体素子によれば、リフロー時にコネクター７が図４
（Ａ）の右方向（矢印Ｙと反対方向）に移動するという
問題があった。つまり、コネクター７のコネクター爪８
は、「Ｈ」形状をした第２のリード２の切欠部２ａに、
第２のリード２を左方向、上下方向に押すように食い込
んでいる（図４（Ａ）参照）が、右方向に対しては何ら
規制していないため、リフロー時に半田層３，５，６の
溶融によりコネクター７が図４（Ａ）の右方向に移動す
る。However, according to the conventional semiconductor device, the connector 7 is not connected during reflow as shown in FIG.
There is a problem of moving to the right of (A) (the direction opposite to arrow Y). That is, the connector claw 8 of the connector 7
Is formed in the notch 2a of the second lead 2 having an "H" shape.
The second lead 2 is bitten so as to be pushed in the left and up and down directions (see FIG. 4A). However, since there is no restriction on the right direction, the solder layers 3, 5, and 6 are not reflowed. As a result, the connector 7 moves rightward in FIG.
【０００７】本発明はこうした事情を考慮してなされた
もので、第２のリードの内側端部と隣接するストッパー
をコネクターに設けた構成にすることにより、リフロー
時にコネクターが移動するのを回避し、もってコネクタ
ーを精度良く位置決めできるコネクター型半導体素子を
提供することを目的とする。[0007] The present invention has been made in view of such circumstances. By providing a connector with a stopper adjacent to the inner end of the second lead, it is possible to prevent the connector from moving during reflow. Accordingly, an object of the present invention is to provide a connector-type semiconductor element capable of accurately positioning a connector.
【０００８】[0008]
【課題を解決するための手段】本発明は、第１のリード
と、この第１のリードと離間するとともに、一部が高さ
方向に第１のリードと段違いに配置された第２のリード
と、前記第１のリード上に半田層を介して搭載された半
導体チップと、この半導体チップ上に半田層を介して形
成され、端部に前記第２のリードと係止するコネクター
爪を有するコネクターと、前記半導体チップを樹脂封止
する外囲器とを具備し、前記コネクターに、前記第２の
リードの内側端部と隣接するストッパーを設けたことを
特徴とするコネクター型半導体素子である。According to the present invention, there is provided a first lead and a second lead which is spaced apart from the first lead and partially arranged in a height difference from the first lead. A semiconductor chip mounted on the first lead via a solder layer; and a connector claw formed on the semiconductor chip via the solder layer and having an end caught with the second lead. A connector-type semiconductor element, comprising: a connector; and an envelope for sealing the semiconductor chip with a resin, wherein the connector is provided with a stopper adjacent to an inner end of the second lead. .
【０００９】[0009]
【発明の実施の形態】以下、本発明について更に詳しく
説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in more detail.
【００１０】本発明において、前記ストッパーとして
は、例えば前記コネクターの一部をカットし、折り曲げ
て成る折り曲げ部、あるいは前記コネクターの一部を押
圧して形成される突起（エンボス）が挙げられるが、こ
れに限定されない。例えば、第２のリードの端部と接す
る位置に対応するコネクターの裏面に、ストッパーとは
別体の突起部材を例えば半田付け、溶接、圧着のいずれ
かにより取り付けた場合も含む。但し、前記折り曲げ部
や突起はリードフレームからリードを形成する際の一連
の工程の中、プレス工程で作ることができるので、作業
性がよい。In the present invention, examples of the stopper include a bent portion formed by cutting and bending a part of the connector, or a protrusion (emboss) formed by pressing a part of the connector. It is not limited to this. For example, a case in which a projection member separate from the stopper is attached to the back surface of the connector corresponding to a position in contact with the end of the second lead by any of, for example, soldering, welding, or crimping. However, since the bent portions and the projections can be formed by a pressing step in a series of steps for forming a lead from a lead frame, workability is good.
【００１１】本発明によれば、コネクターの一部にスト
ッパーを設けることにより、コネクターの上下、左右方
向（図１（Ａ）参照）の位置決めが可能となり、リフロ
ー時にコネクターが移動するのを回避することができ
る。その結果、コネクターの搭載精度が改良されので、
コネクターの移動に起因する遊び代を設ける必要がな
く、製品の小型化を実現することができる。According to the present invention, by providing a stopper on a part of the connector, it is possible to position the connector in the vertical and horizontal directions (see FIG. 1A), and to prevent the connector from moving during reflow. be able to. As a result, the mounting accuracy of the connector is improved,
There is no need to provide play allowance due to the movement of the connector, and the product can be downsized.
【００１２】[0012]
【実施例】以下、本発明の各実施例に係るコネクター型
半導体素子について図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A connector type semiconductor device according to each embodiment of the present invention will be described below with reference to the drawings.
【００１３】（実施例１）図１（Ａ）〜（Ｄ）を参照す
る。ここで、図１（Ａ）は本発明の実施例１に係るコネ
クター型半導体素子の平面図、図１（Ｂ）は図１（Ａ）
のＹ矢視図、図１（Ｃ）は図１（Ａ）のＸ−Ｘ線に沿う
断面図、図１（Ｄ）は同半導体素子の一構成である第２
のリードの平面図を示す。(Embodiment 1) Referring to FIGS. 1A to 1D. Here, FIG. 1A is a plan view of the connector-type semiconductor device according to the first embodiment of the present invention, and FIG.
1C is a cross-sectional view taken along line XX of FIG. 1A, and FIG. 1D is a second configuration of the semiconductor device.
FIG.
【００１４】図中の付番１１は、第１のリードを示す。
この第１のリード１１と離間した位置には、一部が高さ
方向に第１のリード１１と段違いに配置された第２のリ
ード１２が配置されている。ここで、第２のリード１２
は、図１（Ｄ）に示すように平面形状が略「Ｈ」の形を
なしている。前記第１のリード上１１上には、第１の半
田層１３を介して半導体チップ１４が搭載されている。Reference numeral 11 in the drawing denotes a first lead.
At a position separated from the first lead 11, a second lead 12, a part of which is arranged differently from the first lead 11 in the height direction, is arranged. Here, the second lead 12
Has a substantially "H" shape in plan view as shown in FIG. A semiconductor chip 14 is mounted on the first lead 11 via a first solder layer 13.
【００１５】前記半導体チップ１４，第２のリード１２
上には、第２の半田層１５，第３の半田層１６を夫々介
してコネクター１７が接合されている。ここで、コネク
ター７の端部（図１（Ａ），（Ｃ）の右端部）には、前
記第２のリード１２の切欠部１２ａに装着して係止する
コネクター爪１８を有している。また、前記半導体チッ
プ１４との接合面の一部に相当する前記コネクター１７
の一部は、エンボス加工により突起（エンボス）１９が
形成されている。更に、前記第２のリード１２の左端部
に位置する前記コネクター１７には、ストッパーとして
の折り曲げ部２０が設けられている。The semiconductor chip 14 and the second lead 12
A connector 17 is joined on the upper side via a second solder layer 15 and a third solder layer 16. Here, at the end of the connector 7 (the right end in FIGS. 1A and 1C), there is provided a connector claw 18 to be attached to the notch 12a of the second lead 12 and locked. . Further, the connector 17 corresponding to a part of a bonding surface with the semiconductor chip 14 is provided.
Are formed with projections (embosses) 19 by embossing. Further, the connector 17 located at the left end of the second lead 12 is provided with a bent portion 20 as a stopper.
【００１６】前記折り曲げ部２０は、コネクター１７の
一部を切断し、第２のリード１２側に折り曲げることに
より形成されている。そして、その折り曲げ部２０は、
第２のリード１２の左端部１２ｂに接し、コネクター爪
１８と折り曲げ部２０により第２のリード１２の一部を
挟み込んでいる。前記半導体チップ１４、コネクター１
７、第１のリード１１の一部、及び第２のリード１２の
一部は、樹脂製の外囲器２１により封止されている。The bent portion 20 is formed by cutting a part of the connector 17 and bending the connector 17 toward the second lead 12. And the bent part 20 is
A part of the second lead 12 is sandwiched between the connector claw 18 and the bent portion 20 in contact with the left end 12b of the second lead 12. The semiconductor chip 14, the connector 1
7. A part of the first lead 11 and a part of the second lead 12 are sealed by a resin envelope 21.
【００１７】ところで、こうした構成の半導体素子は次
のようにして製作する。まず、第１のリード１１上に第
１の半田層１３を、第２のリード１２上に第３の半田層
１６を夫々同時に形成した。つづいて、第１のリード１
１上に第１の半田層１３を介して半導体チップ１４を搭
載した。次に、半導体チップ１４、前記第２のリード１
２上に、第２の半田層１５，第３の半田層１６を夫々介
して突起１９、折り曲げ部２０を有したコネクター１７
を載せた。このとき、コネクター爪１８が第２のリード
１２の切欠部１２ａに食い込むととももに、折り曲げ部
２０が第２のリード１２の左端部に接する為、折り曲げ
部２０とコネクター爪１８により第２のリード１２の一
部１２ｂを挟み込むことになる。ひきつづき、リフロー
を施し、各半田層１３，１５，１６を融着させ、半導体
チップ１４と第１のリード１１，第２のリード１２同士
を接合した後、モールドを行い外囲器２１を形成した。Incidentally, a semiconductor device having such a configuration is manufactured as follows. First, the first solder layer 13 was formed on the first lead 11 and the third solder layer 16 was formed on the second lead 12 at the same time. Next, the first lead 1
A semiconductor chip 14 was mounted on the semiconductor chip 1 via a first solder layer 13. Next, the semiconductor chip 14, the second lead 1
2, a connector 17 having a projection 19 and a bent portion 20 via a second solder layer 15 and a third solder layer 16 respectively.
Was put. At this time, since the connector claw 18 cuts into the notch 12a of the second lead 12 and the bent portion 20 comes into contact with the left end of the second lead 12, the second portion is formed by the bent portion 20 and the connector claw 18. The part 12b of the lead 12 is sandwiched. Subsequently, reflow was performed, the solder layers 13, 15, and 16 were fused and the semiconductor chip 14 was joined to the first lead 11 and the second lead 12, followed by molding to form an envelope 21. .
【００１８】上記実施例１によれば、コネクター１７の
一部を切断して第２のリード１２側に折り曲げることに
より折り曲げ部２０を形成し、この折り曲げ部２０とコ
ネクター爪１８とにより第２のリード１２の一部を左右
から挟み込む構成となっているため、リフロー時にも半
田層１３，１５，１６の溶融によりコネクター１７が平
面的に見て左右、上下のいずれの向きに移動することを
回避できる。According to the first embodiment, a part of the connector 17 is cut and bent toward the second lead 12 to form a bent part 20, and the bent part 20 and the connector claw 18 are used to form the second part. Since a part of the lead 12 is sandwiched from the left and right, the connector 17 is prevented from moving in the left, right, up or down direction when viewed from above due to the melting of the solder layers 13, 15, 16 even during reflow. it can.
【００１９】なお、上記実施例１では、１つの折り曲げ
部２０が裏面から見て図３（Ａ）に示すように第２のリ
ード１２の端部に沿って全面的に接している場合につい
て述べたが、これに限らず、図３（Ｂ）に示すように２
つの折り曲げ部２０が第２のリード１２の端部に接して
いる場合でもよい。また、図３（Ｃ）に示すように、折
り曲げ部２０が第２のリード１２の端部から若干離間し
ている場合でも、従来と比べ十分な効果が得られる。In the first embodiment, the case where one bent portion 20 is in full contact along the end of the second lead 12 as shown in FIG. However, the present invention is not limited to this, and as shown in FIG.
One bent portion 20 may be in contact with the end of the second lead 12. Further, as shown in FIG. 3C, even when the bent portion 20 is slightly separated from the end of the second lead 12, a sufficient effect can be obtained as compared with the related art.
【００２０】（実施例２）図２（Ａ）、（Ｂ）を参照す
る。ここで、図２（Ａ）は本発明の実施例２に係るコネ
クター型半導体素子の平面図、図２（Ｂ）は図２（Ａ）
の要部の断面図を示す。但し、図１と同部材は同符番を
付して説明を省略する。(Embodiment 2) Referring to FIGS. 2A and 2B. Here, FIG. 2A is a plan view of a connector-type semiconductor device according to a second embodiment of the present invention, and FIG. 2B is a plan view of FIG.
FIG. However, the same members as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.
【００２１】実施例２の半導体素子は、図１の半導体素
子と比べ、折り曲げ部の代わりにコネクター１７の一部
をエンボス加工し、第２のリード１２の左端部に接する
ように突起（エンボス）３０を設けたことを特徴とす
る。その他の点は図１と同様である。ここで、突起３０
は、コネクター１７のコネクター爪１８や突起１９の形
成時に同時に加工することが可能である。The semiconductor device of the second embodiment is different from the semiconductor device of FIG. 1 in that a part of the connector 17 is embossed in place of the bent portion, and a projection (emboss) is provided so as to be in contact with the left end of the second lead 12. 30 is provided. Other points are the same as those in FIG. Here, the protrusion 30
Can be formed simultaneously with the formation of the connector claws 18 and the projections 19 of the connector 17.
【００２２】実施例２によれば、コネクター１７の一部
に第２のリード１２の一部をコネクター爪１８とともに
挟み込む突起３０を設けた構成となっているため、実施
例１と同様な効果が得られる。According to the second embodiment, since the projections 30 for sandwiching a part of the second lead 12 together with the connector claws 18 are provided on a part of the connector 17, the same effects as those of the first embodiment can be obtained. can get.
【００２３】なお、前記突起３０と第２のリード１２の
端部との関係は、図３で述べたようなコネクター１７の
折り曲げ部２０と第２のリード１２との関係と同じこと
が言える。The relationship between the protrusion 30 and the end of the second lead 12 can be said to be the same as the relationship between the bent portion 20 of the connector 17 and the second lead 12 as described with reference to FIG.
【００２４】[0024]
【発明の効果】以上詳述したように本発明によれば、第
２のリードの内側端部と隣接するストッパーをコネクタ
ーに設けた構成にすることにより、リフロー時にコネク
ターが移動するのを回避し、もってコネクターを精度良
く位置決めできるコネクター型半導体素子を提供でき
る。As described above in detail, according to the present invention, the connector is provided with the stopper adjacent to the inner end of the second lead, thereby preventing the connector from moving during reflow. Thus, it is possible to provide a connector-type semiconductor element capable of accurately positioning the connector.
【図１】本発明の実施例１に係るコネクター型半導体素
子の説明図。FIG. 1 is an explanatory diagram of a connector-type semiconductor device according to a first embodiment of the present invention.
【図２】本発明の実施例２に係るコネクター型半導体素
子の説明図。FIG. 2 is an explanatory diagram of a connector-type semiconductor device according to a second embodiment of the present invention.
【図３】本発明のコネクター型半導体素子の変形例の説
明図。FIG. 3 is an explanatory view of a modified example of the connector type semiconductor element of the present invention.
【図４】従来のコネクター型半導体素子の説明図。FIG. 4 is an explanatory view of a conventional connector type semiconductor element.
１１…第１のリード、 １２…第２のリード、 １３，１５，１６…半田層、 １４…半導体チップ、 １７…コネクター、 １８…コネクター爪、 １９ 突起、 ２０…折り曲げ部、 ２１…外囲器、 ３０…突起（エンボス）。DESCRIPTION OF SYMBOLS 11 ... 1st lead, 12 ... 2nd lead, 13, 15, 16 ... Solder layer, 14 ... Semiconductor chip, 17 ... Connector, 18 ... Connector nail | claw, 19 protrusion , 20 ... Bending part, 21 ... Envelope , 30 ... protrusion (emboss).
Claims (3)
間するとともに、一部が高さ方向に第１のリードと段違
いに配置された第２のリードと、前記第１のリード上に
半田層を介して搭載された半導体チップと、この半導体
チップ上に半田層を介して形成され、端部に前記第２の
リードと係止するコネクター爪を有するコネクターと、
前記半導体チップを樹脂封止する外囲器とを具備し、 前記コネクターに、前記第２のリードの内側端部と隣接
するストッパーを設けたことを特徴とするコネクター型
半導体素子。1. A first lead, a second lead that is spaced apart from the first lead, and is partially disposed in the height direction at a level different from the first lead, and a second lead on the first lead. A semiconductor chip mounted on the semiconductor chip via a solder layer, and a connector formed on the semiconductor chip via the solder layer, and having a connector claw at an end portion for engaging with the second lead;
A connector-type semiconductor device, comprising: an envelope for sealing the semiconductor chip with a resin; and wherein the connector is provided with a stopper adjacent to an inner end of the second lead.
部をカットし、折り曲げて成る折り曲げ部であることを
特徴とする請求項１記載のコネクター型半導体素子。2. The connector-type semiconductor device according to claim 1, wherein the stopper is a bent portion formed by cutting and bending a part of the connector.
部を押圧して形成されるエンボスであることを特徴とす
る請求項１記載のコネクター型半導体素子。3. The connector-type semiconductor device according to claim 1, wherein the stopper is an emboss formed by pressing a part of the connector.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000156708A JP3274126B2 (en) | 2000-05-26 | 2000-05-26 | Connector type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000156708A JP3274126B2 (en) | 2000-05-26 | 2000-05-26 | Connector type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001339028A true JP2001339028A (en) | 2001-12-07 |
| JP3274126B2 JP3274126B2 (en) | 2002-04-15 |
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ID=18661462
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000156708A Expired - Fee Related JP3274126B2 (en) | 2000-05-26 | 2000-05-26 | Connector type semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3274126B2 (en) |
Cited By (9)
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|---|---|---|---|---|
| US6849930B2 (en) | 2000-08-31 | 2005-02-01 | Nec Corporation | Semiconductor device with uneven metal plate to improve adhesion to molding compound |
| JP2008041851A (en) * | 2006-08-04 | 2008-02-21 | Hitachi Ltd | Power semiconductor device |
| JP2008108886A (en) * | 2006-10-25 | 2008-05-08 | Fuji Electric Device Technology Co Ltd | Resin-sealed semiconductor device |
| JP2009516389A (en) * | 2005-11-18 | 2009-04-16 | フェアチャイルド セミコンダクター コーポレイション | Semiconductor die package using lead frame and clip, and manufacturing method |
| JP2009267054A (en) * | 2008-04-24 | 2009-11-12 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2012069640A (en) * | 2010-09-22 | 2012-04-05 | Toshiba Corp | Semiconductor device and power semiconductor device |
| US8210878B2 (en) | 2008-05-09 | 2012-07-03 | Tyco Electronics Japan G.K. | Electrical connector |
| US10535587B2 (en) | 2015-02-04 | 2020-01-14 | Stmicroelectronics S.R.L. | Integrated electronic device having a dissipative package, in particular dual side cooling package |
| WO2023189266A1 (en) * | 2022-03-28 | 2023-10-05 | 富士電機株式会社 | Metal wiring board |
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| JP2001127226A (en) * | 1999-10-29 | 2001-05-11 | Fuji Electric Co Ltd | Semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849930B2 (en) | 2000-08-31 | 2005-02-01 | Nec Corporation | Semiconductor device with uneven metal plate to improve adhesion to molding compound |
| KR101410514B1 (en) * | 2005-11-18 | 2014-07-02 | 페어차일드 세미컨덕터 코포레이션 | Semiconductor die package using leadframe and clip and method of manufacturing |
| JP2009516389A (en) * | 2005-11-18 | 2009-04-16 | フェアチャイルド セミコンダクター コーポレイション | Semiconductor die package using lead frame and clip, and manufacturing method |
| US8058107B2 (en) | 2005-11-18 | 2011-11-15 | Cruz Erwin Victor R | Semiconductor die package using leadframe and clip and method of manufacturing |
| JP2008041851A (en) * | 2006-08-04 | 2008-02-21 | Hitachi Ltd | Power semiconductor device |
| JP2008108886A (en) * | 2006-10-25 | 2008-05-08 | Fuji Electric Device Technology Co Ltd | Resin-sealed semiconductor device |
| JP2009267054A (en) * | 2008-04-24 | 2009-11-12 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| US8210878B2 (en) | 2008-05-09 | 2012-07-03 | Tyco Electronics Japan G.K. | Electrical connector |
| JP2012069640A (en) * | 2010-09-22 | 2012-04-05 | Toshiba Corp | Semiconductor device and power semiconductor device |
| CN102412218A (en) * | 2010-09-22 | 2012-04-11 | 株式会社东芝 | Semiconductor device and power semiconductor device |
| US10535587B2 (en) | 2015-02-04 | 2020-01-14 | Stmicroelectronics S.R.L. | Integrated electronic device having a dissipative package, in particular dual side cooling package |
| US10964627B2 (en) | 2015-02-04 | 2021-03-30 | Stmicroelectronics S.R.L. | Integrated electronic device having a dissipative package, in particular dual side cooling package |
| WO2023189266A1 (en) * | 2022-03-28 | 2023-10-05 | 富士電機株式会社 | Metal wiring board |
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