JP2001035988A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2001035988A
JP2001035988A JP11202896A JP20289699A JP2001035988A JP 2001035988 A JP2001035988 A JP 2001035988A JP 11202896 A JP11202896 A JP 11202896A JP 20289699 A JP20289699 A JP 20289699A JP 2001035988 A JP2001035988 A JP 2001035988A
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JP
Japan
Prior art keywords
package
semiconductor device
lead
3a
leads
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Granted
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JP11202896A
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Japanese (ja)
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JP3274661B2 (en
Inventor
Tadayuki Shintani
忠之 新谷
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Nec Kyushu Ltd
九州日本電気株式会社
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Priority to JP20289699A priority Critical patent/JP3274661B2/en
Publication of JP2001035988A publication Critical patent/JP2001035988A/en
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Publication of JP3274661B2 publication Critical patent/JP3274661B2/en
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high package density by improving a structure for directly connecting the leads of the semiconductor device. SOLUTION: A lead 3a fixed on at least one side of a package 4 is limited in a length to the outside end of the package 4. A butting portion 4a of the package 4 is formed by cutting away the end portion of the package 4 where the lead 3a having a limited length is fixed and the lead 3a is exposed at the butting portion 4a. The butting portions of the packages 4 are butted against each other and leads 3a are overlapped each other to connect semiconductors together.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、リードフレームに搭載された半導体素子をパッケージで気密封止してなる半導体装置に関するものである。 The present invention relates to relates to a semiconductor device comprising hermetically sealing the semiconductor element mounted on the lead frame package.

【0002】 [0002]

【従来の技術】従来、この種の半導体装置は、リードフレームに搭載された半導体素子をパッケージで気密封止しており、そのパッケージの周辺からリードが横向きに突き出た構造になっている。 Conventionally, this type of semiconductor device is hermetically sealed semiconductor element mounted on the lead frame in the package, which is from the periphery of the package to leads protruding sideways structure.

【0003】この種の半導体装置は、そのリードを基板の回路パターンに接続して基板に搭載した状態で使用するようになっている。 [0003] The semiconductor device of this type is adapted for use in a state of being mounted on the substrate by connecting the leads to the circuit pattern of the substrate.

【0004】ところで、近年、基板への実装密度を高めることが要求されるようになっている。 [0004] In recent years, so that it is required to increase the packing density of the substrate.

【0005】 [0005]

【発明が解決しようとする課題】しかしながら、従来の上述した半導体装置は、基板に実装された状態での隣接するもの同士が基板の回路パターンを介して接続されるため、実装密度を高めるには限界がある。 [SUMMARY OF THE INVENTION However, the conventional semiconductor device described above, since the adjacent ones in a state of being mounted on the substrate are connected via the circuit pattern of the substrate, to increase the mounting density There is a limit.

【0006】最近では、1個の半導体装置に組込む半導体素子の個数を増やし、かつリードの配置によって本数を増やすことにより、実質的な実装密度を高める工夫がされているが、この構造にしても隣接する半導体装置間には、基板の回路パターンを設ける必要があるため、その実装密度を高めるには限界がある。 [0006] Recently, increase the number of semiconductor elements incorporated into one semiconductor device, and by increasing the number by the arrangement of the leads have been to devise to enhance the substantial packing density, even in this structure between adjacent semiconductor device, it is necessary to provide a circuit pattern of the substrate, to increase its packing density is limited.

【0007】以上の状況を考えると、実装密度を高めるには、基板の回路パターンを廃止すればよいが、現在の半導体装置の構造は、そのリードを基板の回路パターンに接続するものであり、基板の回路パターンを廃止することが不可能である。 [0007] Considering the above situation, to increase the mounting density may be discontinued, the circuit pattern of the substrate, but the structure of the current semiconductor device is to connect the leads to the circuit pattern of the substrate, it is impossible to eliminate the circuit pattern of the substrate.

【0008】本発明の目的は、半導体装置のリード同士を直接接続する構造に改良することにより、実装密度を高める半導体装置を提供することにある。 An object of the present invention, by improving the structure for directly connecting the lead to each other of the semiconductor device is to provide a semiconductor device to increase the mounting density.

【0009】 [0009]

【課題を解決するための手段】前記目的を達成するため、本発明に係る半導体装置は、リードフレームに搭載された半導体素子をパッケージで気密封止してなる半導体装置であって、前記パッケージの端縁部を切欠いてパッケージ同士の突合わせ部を形成し、かつ前記突合わせ部にリードを露出させたものである。 To achieve the above object, according to an aspect of a semiconductor device according to the present invention, there is provided a semiconductor device comprising hermetically sealing the semiconductor element mounted on the lead frame in the package, the package lack edge cut to form a butt portion between the package and is intended to expose the leads to the abutting portion.

【0010】また前記突合わせ部に露出したリード同士を重ね合せた板厚が前記リードフレームの板厚に等しいものである。 [0010] thickness was superposed read together exposed to the abutting portion is equal to the thickness of the lead frame.

【0011】また前記重ね合せたリードは、突き合された前記パッケージで被覆されるものである。 [0011] The superposition leads are those covered by the package butted.

【0012】 [0012]

【発明の実施の形態】以下、本発明の実施の形態を図により説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, will be described with reference to FIG embodiments of the present invention.

【0013】図1(a)は、本発明の一実施形態に係る半導体装置を示す断面図、(b)は、図1(a)に示す半導体装置を組合せた状態を示す断面図である。 [0013] FIG. 1 (a) is a sectional view showing a semiconductor device according to an embodiment of the present invention, (b) is a sectional view showing a state in which a combination of the semiconductor device shown in FIG. 1 (a).

【0014】図1に示す本発明の一実施形態に係る半導体装置は、リードフレームのダイパッド6上に接着剤5 [0014] The semiconductor device according to an embodiment of the present invention shown in FIG. 1, the adhesive on the die pad 6 of the lead frame 5
にて半導体素子1を搭載し、半導体素子1の電極とリードフレームのリード3とをワイヤ2で結線し、これらの周囲を封止樹脂4からなるパッケージで気密封止している。 At mounting the semiconductor element 1, a lead 3 of the electrode and the lead frame semiconductor device 1 is connected by wire 2 is hermetically sealed around them in a package comprising a sealing resin 4.

【0015】本発明の実施形態に係る半導体装置においても従来と同様に、リード3をパッケージ4の周辺から横方向に突き出して設けているが、そのリード3を利用して半導体装置同士を直接接続するようにした点が従来例のものと相違するものである。 [0015] Like the conventional semiconductor device according to the embodiment of the present invention, it is provided projecting laterally lead 3 from the periphery of the package 4, directly connecting a semiconductor device to each other by utilizing the lead 3 point where the way is one which differs from that of the conventional example.

【0016】すなわち図1に示す本発明の実施形態に係る半導体装置においては、パッケージ4の少なくとも1 [0016] That is, in the semiconductor device according to the embodiment of the present invention shown in FIG. 1, at least one package 4
辺に設けたリード3aは、パッケージ4の外端までの長さに制限されており、その制限された長さをもつリード3aが設けられたパッケージ4の端縁部を切欠いてパッケージ同士の突合わせ部4aを形成し、その突合わせ部4aにリード3aを露出させている。 Lead 3a provided on the side is limited to the length of the to the outer end of the package 4, collision between the package lacks an edge portion of the package 4 where the lead 3a is provided with the limited length switching the combined portions 4a are formed, thereby exposing the lead 3a in the butt portion 4a.

【0017】本発明の実施形態では図1(a)に示すように、パッケージ同士の突合わせ部4aに臨むリード3 [0017] As in the embodiment of the present invention shown in FIG. 1 (a), the lead 3 facing the abutting portion 4a between the package
aにハーフエッチングを施して、その板厚を通常のリード厚の半分にして露出させている。 By performing half etching to a, it is exposed to the thickness to half of the normal lead thickness.

【0018】通常使用されているリード厚は125〜1 [0018] The lead thickness, which is commonly used 125-1
50μmであるが、リード3aの露出した部分の板厚は65〜75μm程度になっている。 Is a 50 [mu] m, the thickness of the exposed portions of the lead 3a is in the order of 65~75Myuemu.

【0019】本発明の実施形態では図1(a)に示すように、その制限された長さをもつリード3aが設けられたパッケージ4の端縁部を肉厚方向に切欠き、その底部側にリード3aの上面を露出し、さらにリード3aの板厚を半分にしているため、リード3aは、突合わせ部4 [0019] As in the embodiment of the present invention shown in FIG. 1 (a), notch the edge portion of the package 4 which lead 3a having the limited length is provided on the wall thickness direction, the bottom side order to expose the upper surface of the lead 3a, and further to half the thickness of lead 3a, the lead 3a is abutting portion 4
aの切り立った側壁とパッケージ4の外端縁に沿う縦向きの側壁3b,3cと、縦向きの側壁3b,3c間に位置する横向きの上面3dとの3面が突合わせ部4aに露出することとなる。 And the side wall 3b, 3c of the vertical along the sheer sidewall and the outer edge of the package 4 of a, the side wall 3b of the vertical, the three surfaces of the lateral upper surface 3d located between 3c exposed in butt portion 4a and thus.

【0020】なお、図1(a)に示す例では、パッケージ同士の突合わせ部4aは、パッケージ4の上面側,右面側,前後面側のそれぞれに全面開放しているが、これに限定されるものではなく、半導体装置同士を突合わせる状態により開放の面数及び全面開放,部分開放を適宜変更すればよい。 [0020] In the example shown in FIG. 1 (a), abutting portion 4a between package top side of the package 4, the right side, although fully open to respective front and rear side, are not limited to, rather than shall, number of surfaces and entire open open by state combining collision the semiconductor device to each other, may be appropriately changed partially open.

【0021】図2に示すように2個の半導体装置同士を基板を用いることなく接続するには、図4(a)に示すように一方の半導体装置を表向きに配置し、図4(b) The two semiconductor devices together as shown in FIG. 2 to connect without using a substrate, placed face up one of the semiconductor device as shown in FIG. 4 (a), FIG. 4 (b)
に示すように突合わせ部4aに露出したリード3aの上面3dにノズル10から導電性接着剤7を塗布する。 Applying a conductive adhesive 7 from the nozzle 10 to the upper surface 3d of the lead 3a exposed to the butt portion 4a as shown in.

【0022】更に図4(c)に示すように他方の半導体装置を裏向きに配置し、その両者のリード3aを除く突合わせ部4aに図示しない接着剤を塗布し、2つの半導体装置のリード3aを位置決めしてリード3a同士を3 Furthermore placed face down on the other semiconductor device as shown in FIG. 4 (c), applying an adhesive (not shown) in the butt portion 4a except the lead 3a of both, leads of the two semiconductor devices 3 lead 3a each other to position the 3a
面3b,3c,3dで接合し、かつ突合わせ部4a同士を突合わせる。 Surface 3b, 3c, joined at 3d, and align butt butt portion 4a together. この場合、重ね合せたリード3aは突合わせたパッケージ4により被覆され、その重ね合せたリード3aの板厚はリードフレームの板厚とほぼ等しくなり、2個の半導体装置のパッケージ4の表面が同一面内に整合される。 In this case, lead 3a was superposed is covered by the package 4 abutted, the thickness of lead 3a which combined the overlapped approximately equal to the thickness of the lead frame, the two surfaces of the package 4 of the semiconductor device identical They are aligned in a plane.

【0023】また突合わせたパッケージ4の隙間Sに封止樹脂を流し込んで気密封止し、図2に示すようにパッケージ4の外形を平坦に整える。 Further hermetically sealed by pouring butt sealing resin into the clearance S of the package 4, flat trim the outer shape of the package 4 as shown in FIG.

【0024】半導体装置の種類によってはリードが信号の入出力端子を兼ねるもの、或いは電源或いは接地端子として作用するものがあり、これらのものはリード同士を直接接続することが可能であるため、この種の半導体装置に本発明を適用することにより、基板の回路パターンを介することなく直接接続して半導体装置間の設置スペースを縮小して実装密度を高めることができる。 [0024] which leads depending on the type of semiconductor device also serves as the input and output terminals of the signal, or there is one that acts as a power source or a ground terminal, for these things are possible to connect the lead to each other directly, the by applying the present invention to the seed of the semiconductor device, it is possible to increase the reduction to packaging density the installation space between the semiconductor device directly connected without interposing the circuit pattern of the substrate.

【0025】図1(a)では、リード3aの上面側を露出するようにしたが、パッケージ4の下面側に突合わせ部4aを形成して、リード3aの下面側を露出するようにしてもよく、突合わせるパッケージ4の状態に応じて種々変更すればよいものである。 [0025] In FIG. 1 (a), but so as to expose the upper surface of the lead 3a, to form the abutting portion 4a on the lower surface side of the package 4, be exposed to the lower surface side of the lead 3a well, those that may be variously changed in accordance with the state of the package 4 keying collision.

【0026】図1に示す本発明の一実施形態に係る半導体装置を製造する場合を図3に基づいて説明する。 [0026] will be described with reference to FIG. 3 the case of manufacturing a semiconductor device according to an embodiment of the present invention shown in FIG.

【0027】図3(a)に示すようにリード3aを露出するような金型を用い樹脂封止を行うが、リード3aの上面を露出させるにはハーフエッチングを上面に施し、 [0027] While performing the resin sealing using a mold so as to expose the lead 3a as shown in FIG. 3 (a), subjected to half-etching on the upper surface to expose the upper surface of the lead 3a,
そのハーフエッチング部に合わせた突部8cをもつ上金型8aを使用する。 Using the upper mold 8a having a protrusion 8c tailored to the half etching part.

【0028】上金型8a及び下金型8bは共に露出部を形成できるような脱着式金型パーツを設けた方が良い。 The upper mold 8a and the lower mold 8b is better provided with a removable mold parts, such as together can form an exposed part.

【0029】図3(b)のように金型8a,8bのキャビテイ8d内に樹脂封止を注入し、その樹脂をパッケージ4として気密封止を行う。 The mold 8a as shown in FIG. 3 (b), 8b resin sealing is injected into cavities inside 8d of, it performs a hermetic seal of the resin as a package 4.

【0030】また樹脂の注入を行う際に上金型8aの突部8cを用いて、パッケージ4の端縁部を内側に後退させ、パッケージ4の突合わせ部4aを凹ませて形成する。 Further by using the projection 8c of the upper mold 8a when performing the injection of resin, to retract the edges of the package 4 on the inside, it is formed by recessing the abutting portion 4a of the package 4.

【0031】次に図3(c)のように、露出したリード3aをパッケージ4の端縁でパンチ9を使って切り落とし、図3(d)及び図1(a)に示す形状に成形する。 [0031] Next, as in FIG. 3 (c), the exposed leads 3a cut off with the punch 9 in the edges of the package 4 is molded into the shape shown in FIG. 3 (d) and FIG. 1 (a).

【0032】また本発明の実施形態では、パッケージ4 [0032] In the embodiment of the present invention, the package 4
の一辺に突合わせ部4aを設けたが、これに限定されるものではなく、パッケージ4の各辺に突合わせ部4aを設けるようにしてもよい。 Of is provided with the abutting portion 4a on one side, it is not limited thereto, may be provided abutting portion 4a on each side of the package 4.

【0033】 [0033]

【発明の効果】以上説明したように本発明によれば、半導体装置のパッケージに設けた突合わせ部同士を突合わせ、かつリード同士を重ね合せることにより、基板の回路パターンを用いることなく、半導体装置同士を組合せることができ、基板上のスペースを有効に使用して実装密度を向上させることができる。 According to the present invention as described in the foregoing, alignment butt butt portions provided in the package of the semiconductor device, and by superimposing the lead each other, without using a circuit pattern of the substrate, a semiconductor can combine device together, it is possible to improve the mounting density by effectively using the space on the substrate.

【0034】さらに基板の回路パターンを用いることがないため、レイアウトや基板の重ね方の制限がなくなり、自由度が増すことができる。 Furthermore since there is no possible to use the circuit pattern of the substrate, there is no limitation of overlapping way layout and the substrate, it is possible to increase the degree of freedom.

【0035】さらにICパッケージ同士の接合に関して、露出したリード間に櫛状の金属を介在させて接合させることにより、基板上のレイアウトの自由度が増すことができる。 [0035] Further to the junction between the IC package, by bonding with intervening comb-like metal between the exposed leads, can freedom of layout on the substrate is increased.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】(a)は、本発明の一実施形態に係る半導体装置を示す断面図、(b)は、図1(a)に示す半導体装置を組合せた状態を示す断面図である。 1 (a) is a sectional view showing a semiconductor device according to an embodiment of the present invention, (b) is a sectional view showing a state in which a combination of the semiconductor device shown in FIG. 1 (a).

【図2】本発明の一実施形態に係る半導体装置を組合せた状態を示す平面図である。 Is a plan view showing a state in which a combination of a semiconductor device according to an embodiment of the present invention; FIG.

【図3】本発明の一実施形態に係る半導体装置を製造する場合を工程順に示す断面図である。 3 is a cross-sectional view showing a case of manufacturing a semiconductor device according to an embodiment in the order of steps of the present invention.

【図4】本発明の一実施形態に係る半導体装置を組合せる状態を示す断面図である。 It is a sectional view showing a state of combining the semiconductor device according to an embodiment of the present invention; FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 半導体素子 2 ワイヤ 3,3a リード 4 パッケージ 4a 突合わせ部 1 semiconductor element 2 wires 3,3a lead 4 package 4a abutting portion

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 リードフレームに搭載された半導体素子をパッケージで気密封止してなる半導体装置であって、 前記パッケージの端縁部を切欠いてパッケージ同士の突合わせ部を形成し、かつ前記突合わせ部にリードを露出させたことを特徴とする半導体装置。 1. A semiconductor device comprising hermetically sealing the semiconductor element mounted on the lead frame in the package, to form a butt portion between the package cut away the edge portions of the package, and the butt wherein a exposing the lead mating portion.
  2. 【請求項2】 前記突合わせ部に露出したリード同士を重ね合せた板厚が前記リードフレームの板厚に等しいものであることを特徴とする請求項1に記載の半導体装置。 2. A semiconductor device according to claim 1, wherein the thickness of superposed read together exposed to the abutting portion is equal to the thickness of the lead frame.
  3. 【請求項3】 前記重ね合せたリードは、突き合された前記パッケージで被覆されるものであることを特徴とする請求項1に記載の半導体装置。 Wherein said superposition leads A semiconductor device according to claim 1, characterized in that intended to be covered by the package butted.
JP20289699A 1999-07-16 1999-07-16 Semiconductor device Expired - Fee Related JP3274661B2 (en)

Priority Applications (1)

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JP20289699A JP3274661B2 (en) 1999-07-16 1999-07-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20289699A JP3274661B2 (en) 1999-07-16 1999-07-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2001035988A true JP2001035988A (en) 2001-02-09
JP3274661B2 JP3274661B2 (en) 2002-04-15

Family

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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007035670A (en) * 2005-07-22 2007-02-08 Denso Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007035670A (en) * 2005-07-22 2007-02-08 Denso Corp Semiconductor device
JP4581885B2 (en) * 2005-07-22 2010-11-17 株式会社デンソー Semiconductor device
DE102006032490B4 (en) * 2005-07-22 2014-07-03 Denso Corporation Semiconductor device

Also Published As

Publication number Publication date
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