JPS59232460A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To perform diffusion of high-concentration impurities with high accuracy by using the film part in which an oxide film is formed on a diffusion window for low-concentration impurities, after which an oxide film different in the etching speed is formed in a part of said oxide film by ion implantation. CONSTITUTION:After forming a gate electrode 4, a low-concentration impurity 7 is firstly diffused through an impurity diffusion window A. Next, the films 8 and 10 having a masking effect against ion implantation are formed over the whole surface followed by ion implantation of impurities such as P<+> and As<+> over the whole surface which is then etched. By this ion implantation, etching speed of the surface portion 8 whose film thickness is thin becomes faster than that of the inside wall portion whose film thickness is thick, so that only the oxide film 10 on the inside wall remains. After that, high-concentration impurities 11 are diffused through the windows B shaped by said remaining oxide film 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a semi-η7 semiconductor device, and in particular to a method for manufacturing an MO8 type semiconductor device having excellent characteristics.

[Prior art and its problems]

Conventionally, when a semiconductor element is an integrated circuit, such as a MOS transistor, the size of the element has been reduced by Nl'+scaling in order to improve the characteristics of the element. This reduces the device size, increases the channel concentration, and reduces the drive voltage, resulting in a new transistor with high performance that is proportionally smaller than the original device. However, for example, when the impurity concentration is increased and the junction depth is decreased, the electric field becomes high near the gate electrode and drain, causing the generation of so-called hot electrons and the drop/down pressure of the device. It will have a negative effect on the characteristics. Also, the depth of the bond is 02μ? If it is less than n, the wiring and source will be connected to the power line 16.

The ultimate problem arises that it becomes difficult to establish contact between the drains.

[Purpose of the invention]

The purpose of the present invention is to achieve the above %! It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device that can reduce j1 to Wl, realize a reduction in size, increase the degree of integration, and operate at high speed.

[Summary of the invention]

In the method for manufacturing a semiconductor device, the process for impurity diffusion is performed after the metal mold is removed (7. First, low-concentration impurities are removed, and then ions are implanted on the entire surface. 7. After forming the entire masking film, apply P to the entire surface.
", As+, IJ+, and other impurities are ion-implanted. After this, when the entire surface is etched, the etching rate of the ion-implanted film is several times faster than that of the part (original film) where the ion implantation does not reach. , jII4 reflecting the film shape at the time of film formation is formed on the inner circumferential wall of the impurity diffusion window.This transition lies in the method of manufacturing a semiconductor device that uses high concentration impurities at a wave number. According to the present invention, after forming the gate 'F + It is possible to form a high concentration impurity diffusion layer in a single mask alignment process and with good ellipse, resulting in a smooth contact, suppression of the short channel effect, and the generation of a high electric field region near the drain. 2. A semiconductor device with increased plane-down voltage can be obtained.

[Embodiments of the invention]

Specific embodiments of the present invention will be described below with reference to the drawings. First, as shown in Figure 1 (at), the specific resistance is 5 to 20Ω (
7) A field oxide film 2 is formed on the P-type silicon substrate 1 according to the usual process, and a P upper layer 3 for preventing field inversion is formed below it. Thereafter, a gate oxide film 4 having a thickness of 300λ is formed in an oxygen atmosphere at, for example, 900° C., and a polycrystalline silicon film 5 having a thickness of 3000° is formed by the LP CVD method.

Next, as shown in FIG. 1(b), using a resist film 6 formed by photolithography as a mask, for example, starting with C12/■-
The polycrystalline silicon film 5 is etched by the reactive ion etching method using 12 gases, and then the gate oxide film 4 is etched by changing the etching rate to CH4/H2.After this, for example, elemental ions (As+ ) Total Karo speed ton If 40Kev unwamono concentration IXI O” “cm”
A shallow n layer 7 is formed by implantation. After removing the resist film 6, as shown in FIG. 1 (C1), a film having a suitable blocking ability against ion implantation, such as a silicon oxide film 8, is formed to a thickness of 0.4 μm by, for example, the LPCVD method. After that, for example, boron ion (B+) 9 e acceleration voltage 1201 (e v, impurity γ7c degree 5 cut o19 (7)
Ion implantation is performed on the entire surface at -3. At this time, a portion 1° of the silicon oxide film 8 (field [side wall portion of the silicon oxide film 2, gate oxide film 4, and polycrystalline silicon film 5] has the same film thickness as viewed from the boron ion implantation direction. Since the silicon oxide film 8 is thicker, the ion-implanted boron cannot reach it. After this, when the entire surface is etched using a reactive ion etching method using, for example, CFs74-12f etching gas, as shown in FIG. 1o is formed. This takes advantage of the phenomenon that a damaged layer created by ion implantation increases the etching rate; by the way, the etching rate increases by 3 to 4 times due to ion implantation. In this case, the etching rate is as high as the silicon oxide film 10 (ion-implanted silicon oxide film 8 is formed as shown in the figure. After that, for example, phosphorus ions (P+) are implanted at an acceleration voltage of 160 Kev and an impurity concentration of 2 x 1018 cm-" to form a source/drain layer. A layer 11 that will become another wiring layer is formed.After this, a heat treatment is performed for activation, and shallow junctions with low concentration are obtained in the gate region around the impurity injection layer and the region surrounded by the field region. The redistribution of the diffusion layer in the lateral direction can also be minimized.On the other hand, in regions far from the periphery, the concentration is high and a bonding layer 11 deeper than the periphery is obtained.After this, as shown in FIG. PSGll by CVD method
I12 is deposited, contact holes are opened, and lead electrodes, such as aluminum (AI) 13%, are arranged to complete the process.

According to this embodiment, an impurity doping control film serving as an ion implantation mask is formed in the stepped portion surrounding the n+ layer region, and the impurity ion implantation is performed twice by changing the implantation depth and concentration, thereby forming the n+1M layer. Therefore, impurity layers having different junction depths and concentrations can be formed at the periphery and the center. Therefore, since a single layer with a low concentration and a shallow junction depth is required adjacent to the gate oxide film, the spread of the depletion layer from the drain side is small, which makes it possible to significantly suppress the short channel effect. By reducing the occurrence of electric field disturbances near the drain, it has become possible to increase the breakdown voltage.

On the other hand, in the n4- region at the center, the concentration is high and a relatively deep junction is formed, so ohmic contact with the lead-out 'it electrode at the contact part is made good, and defects such as penetration of the electrode material are prevented. Also field oxidation 11#,
And as a method of forming silicon oxide on the sidewalls of the gate region, abnormal etching of the damaged layer created by ion implantation (etching rate is -4) is used, so the ion implantation conditions are changed. By changing the etching shape, the processed shape of Cφ can be controlled arbitrarily, and since the ion-implanted silicon film has an etching selectivity of 3 to 4 times that of the original film, the etching time can be shortened and the device Damage caused can also be reduced.This is due to surface treatment (a step of removing the damaged layer generated on the silicon substrate surface by reactive ion etching) that is conventionally performed after reactive ion etching.
Encourage the Ministry to shorten the process.

Although a silicon oxide film is used in this practical example, any other film that has a masking effect for ion implantation may be used, such as a polycrystalline silicon film, silicon nitride film, or resin. In addition to B+ in the example, 〇9N''-, Ar''-, He
It may be any element that does not cause the risk of contaminating the entire device, such as ", P snow, As", etc. Furthermore, as an etching method for forming a film on the Jill wall, in this embodiment, conventional 1 (Jill wall view) is used.
However, the conventional method uses only anisotropic etching of the reactive ion etching method for three side walls 9A≧". In contrast, the present invention has the following features: Since it utilizes abnormal etching (the etching speed becomes faster) of the damaged layer due to ion implantation, the same shape can be obtained not only by anisotropic etching methods but also by isotropic etching methods.Also, wet etching methods, The same applies to the dry etching method.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 fa) to 1 tel are process cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. 1 Silicon substrate, 2 Field oxide film, 3P+ layer (anti-inversion layer), 4 Gate oxide film, 5 Polycrystalline silicon) 1 A, 6 Resist film, 7 N/N (shallow diffusion layer), 871J Con oxidation Membrane, 913+ ion, 10 silicon oxide film, 11-n soil layer (deep diffusion 1 (4), 12 Pso film, 13 aluminum electrode. (7317) Patent attorney Chika Ichi (and 1 other person)
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Claims (1)

[Claims] (Il) A process in which a gate electrode is formed via a gate insulating film in the element formation region surrounded by a field insulating film of a semiconductor substrate, and then all impurities are diffused through an impurity diffusion window to form a source and a drain. In the manufacturing method of + after forming the gate electrode for diffusion of the impurity.
ii. Low substrate impurity in T-period substrate? Diffusion formation of area A,
Next, after an insulating film is completely formed on the entire surface of this substrate, ions are implanted into the entire surface of the insulating film, and etching is performed on the entire surface so that the gate electrode and the electrode 1t<+
+ A method for manufacturing a semi-43 body 16, comprising the steps of processing and forming a border film on the wall, and then diffusing and forming a high concentration impurity region on the substrate.