JPS58182877A - Manufacture of vertical field effect transistor - Google Patents
Manufacture of vertical field effect transistorInfo
- Publication number
- JPS58182877A JPS58182877A JP6534582A JP6534582A JPS58182877A JP S58182877 A JPS58182877 A JP S58182877A JP 6534582 A JP6534582 A JP 6534582A JP 6534582 A JP6534582 A JP 6534582A JP S58182877 A JPS58182877 A JP S58182877A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- gate
- source
- region
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000005669 field effect Effects 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 3
- 239000011574 phosphorus Substances 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- -1 boron ions Chemical class 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は縦型電界効果トランジスタ（縦型ＦＥＴ）の製
造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a vertical field effect transistor (vertical FET).
縦型ＦＥＴの製造方法として、第１図（ａ）〜（Ｃ）で
示す方法が知られている。すなわち、この方法では、Ｎ
−型のシリコン半導体基板１の主面（土面）を絶縁膜２
で被った後、フォトエツチングによって絶縁膜２を部分
的に除去してゲート形成用窓３を開ける。その後、不純
物（ボロン）を拡散して露出する半導体基板１０表層部
にＰ＋型のゲート領域４を形成する。As a method for manufacturing a vertical FET, the method shown in FIGS. 1(a) to 1(C) is known. That is, in this method, N
- The main surface (soil surface) of the type silicon semiconductor substrate 1 is covered with an insulating film 2.
After that, the insulating film 2 is partially removed by photoetching to open the gate forming window 3. Thereafter, an impurity (boron) is diffused to form a P+ type gate region 4 in the exposed surface layer of the semiconductor substrate 10.
つぎに、同図（ｂ）で示すように、半導体基板１０表面
の絶縁膜２をエツチング除去した後、エピタキシャル層
５を半導体基板１の主面に成長させる。Next, as shown in FIG. 2B, after the insulating film 2 on the surface of the semiconductor substrate 10 is removed by etching, an epitaxial layer 5 is grown on the main surface of the semiconductor substrate 1.
この結果、ゲート領域４は埋込層となる。As a result, gate region 4 becomes a buried layer.
その後、再び絶縁膜６でエピタキシャル層５上を被うと
ともに、フォトエツチングによって絶縁膜６を部分的に
除去してソース形成用窓を形成し。Thereafter, the epitaxial layer 5 is again covered with an insulating film 6, and the insulating film 6 is partially removed by photo-etching to form a source forming window.
Ａｓ （砒素）、Ｐ（燐）等の不純物を、露出するエピ
タキシャル層５０表層部に拡散させてＮ＋型のソース領
域７を形成する。さらに、ソース電極８あるいは図示し
ないゲート電極、ドレイン電極を形成して縦型ＦＥＴを
製造する。Impurities such as As (arsenic) and P (phosphorus) are diffused into the exposed surface layer of the epitaxial layer 50 to form an N+ type source region 7. Further, a source electrode 8 or a gate electrode and a drain electrode (not shown) are formed to manufacture a vertical FET.
ところで、この製造方法では、エビタギシャル層５の形
成時に、熱によってゲート領域４に拡散されたボロン（
Ｂ）がアウトディフュージョンするため、オートドーピ
ング現象が発生し易い。このため、第２図に示すように
、エピタキシャル層５の下層には点点で示すようにボロ
ンを含む層が形成され、離れた位置にあるゲート領域４
間の電気的リークが発生したり、電気的に導通状態とし
てしまい、歩留の低下を来たしてしまう難点がある。By the way, in this manufacturing method, boron (
Since B) outdiffuses, an autodoping phenomenon is likely to occur. Therefore, as shown in FIG. 2, a layer containing boron is formed below the epitaxial layer 5 as shown by dots, and the gate region 4 located at a distance is formed.
There are disadvantages in that electrical leakage may occur between the two, or electrical conduction may occur, resulting in a decrease in yield.
したがって、本発明の目的は歩留が高い縦型電界効果ト
ランジスタの製造方法を提供することにある。Therefore, an object of the present invention is to provide a method for manufacturing vertical field effect transistors with high yield.
このような目的を達成するために本発明は、縦型電界効
果トランジスタのｊＭ造方法において、第１導電型の半
導体基板の主面を絶縁膜で被うとともにソース・ゲート
形成用窓を開ける工程と、ソース形成用窓を前記絶縁膜
とは異なるマスキング物質膜で被う工程と、ゲート形成
領域に不純物を拡散させるとともに表面を酸化膜で被っ
た第２導電型のゲート領域を形成する工程と、前記マス
キング物質膜を除去するとともにソース形成領域に不純
物を拡散させて前記半導体基板よりも高濃度の第１導電
型のソース領域を形成する工程と、を有するものであっ
て、以下実施例により本発明を説明する。In order to achieve such an object, the present invention provides a step of covering the main surface of a semiconductor substrate of a first conductivity type with an insulating film and opening windows for forming source and gate in a JM manufacturing method of a vertical field effect transistor. a step of covering the source formation window with a masking material film different from the insulating film; and a step of diffusing impurities into the gate formation region and forming a second conductivity type gate region whose surface is covered with an oxide film. , removing the masking material film and diffusing impurities into the source formation region to form a source region of a first conductivity type with a higher concentration than the semiconductor substrate. The present invention will be explained.
第３図（ａ）〜（ｅｅｌは本発明の一実施例による縦型
電界効果トランジスタの製造方法を示す断面図である。FIGS. 3A to 3E are cross-sectional views showing a method of manufacturing a vertical field effect transistor according to an embodiment of the present invention.
同図（ａ）に示すように、Ｎ〜型（第１導電型）のシリ
コン半導体基板１０の主面（上面）にＳ ｉ Ｏ。As shown in FIG. 5A, SiO is formed on the main surface (top surface) of an N-type (first conductivity type) silicon semiconductor substrate 10.
膜からなる絶縁膜１１（厚さ６０００〜７０００Ａ）を
形成するとともに、フォトエツチングによって絶縁膜１
１を部分的にエツチングしてソース形成窓１３およびゲ
ート形成窓１３を開ける。この際、１対のゲート形成領
域間（Ｌ）は５μｍ程度となる。An insulating film 11 (thickness 6000 to 7000 A) consisting of a film is formed, and the insulating film 11 is formed by photoetching.
1 is partially etched to open a source forming window 13 and a gate forming window 13. At this time, the distance (L) between the pair of gate formation regions is approximately 5 μm.
つぎに、同図（ｂ）に示すように、半導体基板１０の主
面全域にポリシリコン膜１４を５００ＯＡの厚さに形成
するとともに、フォトエツチングによってポリシリコン
膜１４を部分的にエツチング除去し、ゲート形成窓１３
を露出させる。この際、ソース形成窓１２はポリシリコ
ン膜１４で被われる。Next, as shown in FIG. 2B, a polysilicon film 14 is formed to a thickness of 500 OA over the entire main surface of the semiconductor substrate 10, and the polysilicon film 14 is partially etched away by photo-etching. Gate forming window 13
expose. At this time, the source forming window 12 is covered with a polysilicon film 14.
このポリシリコン膜１４は次のイオン打込みによって、
不純物がソース形成領域に打ち込まれるのを阻止するに
充分な厚さとなっている。また、ポリシリコン膜１４０
部分エツチングは残留するポリシリコン膜１４の縁が絶
縁膜１１上に位置させればよいことから、フォトエツチ
ングの精度はそれ程高くなくともよい。This polysilicon film 14 is formed by the next ion implantation.
The thickness is sufficient to prevent impurities from being implanted into the source formation region. In addition, the polysilicon film 140
In partial etching, the edge of the remaining polysilicon film 14 only needs to be located on the insulating film 11, so the accuracy of photoetching does not need to be very high.
つぎに、ボロンをイオン打込みによって露出する半導体
基板１０のゲート形成領域に打ち込んだ後、引延し拡散
を行ない、４〜５μｍの深さのＰ型のゲート領域１５を
形成する。この際、ゲート領域１５０表面は引延し拡散
時の熱によって酸化膜１６が生成される（同図（Ｃ）参
照）。Next, boron is implanted into the exposed gate formation region of the semiconductor substrate 10 by ion implantation, and then stretched and diffused to form a P-type gate region 15 with a depth of 4 to 5 μm. At this time, the surface of the gate region 150 is stretched and an oxide film 16 is generated by the heat during the diffusion (see FIG. 2C).
つぎに、同図（ｄ）で示すように、砒素あるいは燐をイ
オン打込みして、露出する半導体基板１０のソース形成
領域に０．５μｍの深さに打ち込み、半導体基板１０よ
りも高濃度となるＮ＋型のソース領域１７を形成する。Next, as shown in FIG. 2D, arsenic or phosphorus is ion-implanted into the exposed source formation region of the semiconductor substrate 10 to a depth of 0.5 μm, so that the concentration is higher than that of the semiconductor substrate 10. An N+ type source region 17 is formed.
その後、同図（ｅ）に示すように、アルミニウムおよび
シリコンからなるソース電極１８および図示しないゲー
ト電極ならびにドレイン電極を形成し、縦型ＰＥＴを製
造する。Thereafter, as shown in FIG. 3(e), a source electrode 18 made of aluminum and silicon, and a gate electrode and a drain electrode (not shown) are formed to manufacture a vertical PET.
このような方法によれば、埋込層の形成のためのエピタ
キシャル成長処理作業は不必要となることから、オート
ドーピングによるリーク電流の発生、あるいはゲート領
域間の導通（ショート）による特性不良は生じない。こ
のため、歩留が向上する。According to this method, there is no need for epitaxial growth processing to form a buried layer, so leakage current due to autodoping or characteristic defects due to conduction (short) between gate regions does not occur. . Therefore, the yield is improved.
また、この方法によれば、ゲート領域とソース領域はセ
ルファライン（自己整合）によって形成されるため、両
領域が重なるようなこともなく入力容量が過大になる様
な、製造バラツキも押えられる。Further, according to this method, since the gate region and the source region are formed by self-alignment, the two regions do not overlap, and manufacturing variations such as excessive input capacitance can be suppressed.
なお、本発明は前記実施例に限定されない。すなわち、
ソース形成領域な一時的に被うマスキング物質はポリシ
リコン以外の物質、たとえばシリサイドでもよい。また
、ポリシリコンとシリサイドの２層構造であってもよい
。このマスキング物質は絶縁膜とは異なるエッチャント
によってエツチングされる物質を選ぶ必要がある。Note that the present invention is not limited to the above embodiments. That is,
The masking material that temporarily covers the source formation region may be a material other than polysilicon, such as silicide. Alternatively, it may have a two-layer structure of polysilicon and silicide. This masking material needs to be selected from a material that is etched by a different etchant from that of the insulating film.
以上のように、本発明によれば、歩留が高く信頼性の高
い縦型電界効果トランジスタの製造方法を提供すること
ができる。As described above, according to the present invention, it is possible to provide a method for manufacturing a vertical field effect transistor with high yield and high reliability.
第１図（ａ）〜（Ｃ）は従来の縦型Ｆ Ｅ Ｔの製造方
法の一部を示す断面図、第２図は同じく不良製品の断面
図、第３図（ａ）〜（ｅ）は本発明の一実施例による縦
型ＦＥＴの製造方法の一部を示す断面図である。
１０・・・半導体基板、１２・・・ソース形成窓、１３
・・・ゲート形成窓、１４・・・ポリシリコン膜、１５
・・ゲート領域、１７ ・ソース領域、１８・・・ソー
ス醒極。Figures 1 (a) to (C) are cross-sectional views showing part of the conventional vertical FET manufacturing method, Figure 2 is a cross-sectional view of a similarly defective product, and Figures 3 (a) to (e). 1 is a cross-sectional view showing a part of a method for manufacturing a vertical FET according to an embodiment of the present invention. 10... Semiconductor substrate, 12... Source formation window, 13
...Gate formation window, 14...Polysilicon film, 15
...Gate region, 17 - Source region, 18... Source awakening.
Claims (1)
１導電型の半導体基板の主面を絶縁膜で被うとともにソ
ース・ゲート形成用窓を開ける工程と、ソース形成用窓
を前記絶縁膜とは異なるマスキング物質膜で被う工程と
、ゲート形成領域に不純物を拡散させるとともに表面を
酸化膜で被った第２導電型のゲート領域を形成する工程
と、前記マスキング物質膜を除去するとともにソース形
成領域に不純物を拡散させて前記半導体基板よりも高濃
度の第１導ｗ型のソース領域を形成する工程と、を有す
ることを特徴とする縦型電界効果型トランジスタの製造
方法。1. A method for manufacturing a vertical field effect transistor, including the steps of: covering the main surface of a first conductivity type semiconductor substrate with an insulating film and opening a window for forming a source/gate; a step of covering the gate region with a different masking material film, a step of diffusing impurities into the gate formation region and forming a second conductivity type gate region whose surface is covered with an oxide film, and a step of removing the masking material film and removing the source formation region. A method for manufacturing a vertical field effect transistor, comprising the step of: diffusing impurities into the semiconductor substrate to form a first conductive w-type source region having a higher concentration than the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6534582A JPS58182877A (en) | 1982-04-21 | 1982-04-21 | Manufacture of vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6534582A JPS58182877A (en) | 1982-04-21 | 1982-04-21 | Manufacture of vertical field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58182877A true JPS58182877A (en) | 1983-10-25 |
Family
ID=13284262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6534582A Pending JPS58182877A (en) | 1982-04-21 | 1982-04-21 | Manufacture of vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182877A (en) |
-
1982
- 1982-04-21 JP JP6534582A patent/JPS58182877A/en active Pending
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