JPS59229952A - Signal transmitting method - Google Patents

Signal transmitting method

Info

Publication number
JPS59229952A
JPS59229952A JP10460983A JP10460983A JPS59229952A JP S59229952 A JPS59229952 A JP S59229952A JP 10460983 A JP10460983 A JP 10460983A JP 10460983 A JP10460983 A JP 10460983A JP S59229952 A JPS59229952 A JP S59229952A
Authority
JP
Japan
Prior art keywords
signal
master device
receiver
control circuit
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10460983A
Other languages
Japanese (ja)
Inventor
Masakazu Yokoi
横井 正和
Katsuhisa Hagami
勝久 葉上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tsubakimoto Chain Co
Original Assignee
Tsubakimoto Chain Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tsubakimoto Chain Co filed Critical Tsubakimoto Chain Co
Priority to JP10460983A priority Critical patent/JPS59229952A/en
Publication of JPS59229952A publication Critical patent/JPS59229952A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To reduce the load on a transmitter by providing a master device capable of transmission and reception, and generating a check sum code on the basis of a reception signal and transmitting it to a receiver. CONSTITUTION:Numbers of transmitters T1-Tn and receivers R1-Rn are connected to common transmission lines l1 and l2, and the master device M capable of transmissin and reception is connected. When some of the transmitters, e.g. T1 sends a bit-serial signal to the transmission lines l1 and l2, the address-specified receiver T2 fetches the signal in a specific register of its control circuit. The master device M, on the other hand, fetches it in its control circuit 2 and calculates the check sum code to send out a serial signal of the receive signal to the transmission lines l1 and l2. The receiver R2 receives the signal to perform a sum check, and validates the signal fetched in the register when normal. A specific resending request signal is generated when abnormal.

Description

【発明の詳細な説明】 本発明は時分割方式の信り伝送方法に関し、四に詳述−
′rhば、サムチェックを行わしめて伝送信号の信頼性
を高めた信号伝送方法を提案でるものである。
[Detailed Description of the Invention] The present invention relates to a time-division trust transmission method, which will be described in detail in Section 4-
In other words, it is possible to propose a signal transmission method that improves the reliability of the transmitted signal by performing a sum check.

複数の装置間にて信号伝送を行う場合、伝送中でのデー
タ欠落等によるトラブルを避けるために種々のデータチ
ェックが行われる。このデータチェックは送信側装置と
受信側装置とがl対Iに対応している場合にはサムチェ
ック、CRC等高級なチェックが行われるが、複数の送
信器、受信器がパーティライン接続されていて信号伝送
を時分割方式にて行う場合は、種々の理由によりパリテ
ィチェック等低級なチェックしか行われていないのが実
情であった。
When transmitting signals between a plurality of devices, various data checks are performed to avoid troubles such as data loss during transmission. This data check is performed using advanced checks such as sum check and CRC when the transmitter and receiver have an I:I correspondence, but if multiple transmitters and receivers are connected by party line, In reality, when signal transmission is performed in a time-division manner, only low-level checks such as parity checks are performed for various reasons.

不発りJは斯かる事情に鑑みてなされたものであって、
送信器に負担を課すことなく、パーティライン接続され
た複数の送、受信器間の信号伝送にサムチェックを行わ
しめて、信号の信頼性ケ制め得る信号伝送方法を提供す
ることを目的とする〇不発Ff4VC係る信号伝送方法
は、共通のラインに接続された複数の送、受信器間にて
信号を時分割的に伝送する方法において、送受信可能な
マスター器を設け、該マスター器は他の送信器が特定の
受信器に発した送信値8を受信[、この受信信号に基づ
きチェックツムコード全作成し、該チェツタサムコード
全前記受信器へ送信することを特徴とする。
The non-explosion J was made in view of such circumstances,
The purpose of the present invention is to provide a signal transmission method that can check the reliability of signals by performing a sum check on signal transmission between a plurality of transmitters and receivers connected through a party line without imposing a burden on the transmitter. 〇The signal transmission method related to unexploded Ff4VC is a method of time-divisionally transmitting signals between multiple transmitters and receivers connected to a common line, in which a master device capable of transmitting and receiving is provided, and the master device The present invention is characterized in that a transmitter receives a transmission value 8 sent to a specific receiver, generates a checksum code based on this received signal, and transmits all the checksum codes to the receiver.

以下本発明を具体的に説明する。第1図は本発男を適用
すべき信号伝送システムの金杯構成番略示するブロック
図であって、2本の伝送線11,12に多数の送信器T
、 、 T2・・・Tn及び受信器R1,R2・・・R
nが接続され、捷た送受信が共に可能なマスター器Mが
接続されている。
The present invention will be specifically explained below. FIG. 1 is a block diagram schematically showing the configuration of a signal transmission system to which the present invention is applied.
, , T2...Tn and receivers R1, R2...R
A master device M, which is capable of both transmitting and receiving signals, is connected.

第2図はマスター器Mの回路構成を示すブロック図であ
る。伝送すべき信号等全外部装置(図示せず)から入力
し、またこの外部装置への応答信号を発したりするため
の入力インターフェースlはマスター器Mの制御中骸と
なるコン斗ロール回1i32に接続されており、該コン
トロール回路2は外部装置から入力された信号を伝送に
適した形態に加工して、これ全送受信回路3を経て伝送
線4゜I!2に送出し、また他の送信器T1. T、・
・・T、が特定の受信器R,、R3・・・Rnへ送信し
た信りを送受信回路3ヲ介して受信し、この受信信号に
チェックサムのための加工を施して該当受信器へ送信す
る。その他4は送信信号のフォーマット指定のためのフ
ォーマット設定回路、5はシステム全体の同期をとるた
めのタロツクを発生する同期クロック回路で第3図は送
信器の構成を示し、前同様の入力インク−7エース11
.と、コントロール回1tR12と、送信回路13と、
前同様のフォーマット設定回路14とからなり、コント
ロール回@12は入力インターフェース11を介して外
部装置(図示せず)から入力された信号全設定されたフ
ォーマット(フォーマットハシステム全体で共通)に加
工して送信器@13を経て伝送線I!1+7?2に送出
する。この送出信号vctriこれを受信させるべき受
信器全特定するコードが付されており、該当受信器がこ
の信号を有効に収込む外、前記マスター器Mもこれ全送
受信回1i!f15B’i介してコントロール回路2に
収込む。
FIG. 2 is a block diagram showing the circuit configuration of the master device M. The input interface l for inputting signals to be transmitted from all external devices (not shown) and for emitting response signals to the external devices is connected to the control circuit 1i32, which is the control body of the master device M. The control circuit 2 processes signals input from an external device into a form suitable for transmission, and sends the signals through the transmission/reception circuit 3 to the transmission line 4°I! 2 and another transmitter T1. T,・
...T receives the signal sent to specific receivers R,, R3...Rn via the transmitting/receiving circuit 3, processes this received signal for checksum, and transmits it to the corresponding receiver. do. In addition, 4 is a format setting circuit for specifying the format of the transmission signal, 5 is a synchronization clock circuit that generates a tally clock for synchronizing the entire system, and FIG. 3 shows the configuration of the transmitter. 7 ace 11
.. , the control circuit 1tR12, the transmission circuit 13,
The control circuit @12 processes all signals inputted from an external device (not shown) through the input interface 11 into a set format (the format is common to the entire system). Transmission line I! via transmitter @13! Send to 1+7?2. This transmission signal vctri is attached with a code that specifies all the receivers that are to receive it, and in addition to the corresponding receivers effectively receiving this signal, the master device M also receives this signal for all transmission and reception times 1i! It is stored in the control circuit 2 via f15B'i.

受信器の構成は第4図に示す如くなっており、伝送線1
..12に連なる受信回路23、コントロール回路22
、外部装置との出力インターフェース21及びフォーマ
ット設定回路24からなる。コ   □ントロール回路
22は受信信号をデコードする等の処理全行い、出力イ
ンターフェース21を介して外部装置へ用カする外、後
述するようにサムチェックを行う。
The configuration of the receiver is as shown in Figure 4, with transmission line 1
.. .. Receiving circuit 23 and control circuit 22 connected to 12
, an output interface 21 with an external device, and a format setting circuit 24. The control circuit 22 performs all processing such as decoding the received signal, sends it to an external device via the output interface 21, and performs a sum check as described later.

なおマスター器Mの外に送受信機能を兼備するモノが接
続されていてもよい。
Note that a device having transmitting and receiving functions may be connected outside the master device M.

而して新かる構成のシステムにおいて本発明ハ次のよう
に実施される。即ちいずれかの送信器、例えばT□が第
5図(イ)に示す如きフォーマットのビットシリアルの
信号を送出したものとする。この送信器T□から発せら
れる信号には固定された宛先(例えば受信器R2)を特
定する情報を含んでいる。
The present invention is implemented in the newly constructed system as follows. That is, it is assumed that some transmitter, for example T□, sends out a bit serial signal in the format shown in FIG. 5(a). The signal emitted from this transmitter T□ contains information specifying a fixed destination (for example, receiver R2).

このような信号が伝送線1r+’12に送出されると、
受信器R2triその受信回路23を介してコントロー
ル回路220所定レジスタに取込む。
When such a signal is sent to the transmission line 1r+'12,
The receiver R2tri takes in the data into a predetermined register of the control circuit 220 via its receiving circuit 23.

一方、マスター器もこれを送受信回路3を介しテコント
ロール回路2へ取込む。そしてこの受信信号につきチェ
ックサムコード全算出し、第5図(ロ)K示す如く受信
信号及びチェックサムコードを一連とした信号を送受信
回路3を介して伝送線/I’1l12へ送出する。そう
すると受信器R,Jtこの信号を受信してコントロール
回f622内の他のレジスタに格納する。そしてコント
ロール回路22けこの受信信号につきサムチェック全行
い、これが正常であると判断した場合は先にレジスタに
収込んでおいた信号を有効化し、これに対応する処理を
実行する。これに対してサムチェックの結果が異常であ
った場合はコ゛□ントロール回路22け所定の再送要求
信号を発し、送信器TIはこれに応答して信号全再送す
る。コントロール回路22は所定回数に亘りす1=F−
ニック異常があった場合[は所定警報信号全外部装置i
it又けその付属回路に発する。
On the other hand, the master device also takes this into the control circuit 2 via the transmitter/receiver circuit 3. Then, all checksum codes are calculated for this received signal, and a signal consisting of a series of received signals and checksum codes is sent to the transmission line /I'112 via the transmitter/receiver circuit 3, as shown in FIG. 5(b)K. Then, the receivers R and Jt receive this signal and store it in another register in the control circuit f622. Then, the control circuit 22 performs a complete sum check on the received signals, and if it is determined to be normal, it validates the signal previously stored in the register and executes the corresponding process. On the other hand, if the result of the sum check is abnormal, the control circuit 22 issues a predetermined retransmission request signal, and in response, the transmitter TI retransmits the entire signal. The control circuit 22 performs the control circuit 22 for a predetermined number of times.
If there is a Nick abnormality, a predetermined alarm signal is sent to all external devices.
It also emits to the attached circuit.

一方、マスター器M自体が信号全伝送する場合汀その信
号につき自らチェックサムコードを算出してこれを信号
に付加して所定受信器を宛先として伝送線l!、 、 
22へ送出する。これにより全伝送信号がサムチェック
されることになる。
On the other hand, when the master device M itself transmits all the signals, it calculates a checksum code for the signal itself, adds it to the signal, sends it to the specified receiver, and sends it to the transmission line l! , ,
22. This results in a sum check of all transmitted signals.

以上の如き本発明方法による場合は各送信器にはサムチ
ェックのための負担を何ら課すことなくサムチェック全
行うことができ、そのコントロール回路12に、より重
要な又は高速性を要する仕事を行わせることが可能とな
る。その分マスター器Mの負担は増すが、マスター器M
’を送出すべき信号の発生頻度が低い外部袋@に関連す
る送信用としておく場合は、システム全体として合理的
稼動が行えることとなる。
In the case of the method of the present invention as described above, each transmitter can perform all the sum checks without imposing any burden for the sum check, and the control circuit 12 can perform more important work or work that requires high speed. It becomes possible to The burden on master device M increases accordingly, but master device M
If ' is used for transmission related to the external bag @ where the frequency of occurrence of the signal to be transmitted is low, the system as a whole can be operated rationally.

以上のように不発明方法による場合はサムチェックによ
って信頼性全高めた信号伝送が比較的簡単な構成で実現
できる。
As described above, in the case of the uninvented method, signal transmission with highly improved reliability can be realized with a relatively simple configuration by means of the sum check.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を適用すべき信号伝送システムの全体構
祿図、第2図はマスター器の回路構成を示すブロック図
、第8図は送信器の回路構成を示すブロック図、第4図
は受信器の回路構成を示すブロック図、第5図は伝送信
号のフォーマット図である。 M・・・マスター器 ′r1. T2・・・Tn ・・
送信器R,,R2・・・1く。・・・受信器 特許出願人 株式会社椿木チェイン 代理人 弁理士 河 野 登 犬 第3 図 第!5図 手 続 補  正  書 (自発) 昭和58年8月5日 2 発明の名称  信号伝送方法 3 補止をする者 事件との関係  特許出願人 所在地    大阪市鶴見区鶴見4丁目17番88号名
 称    (335)  株式会社 椿木チェイン代
表者 占 都 友 − ダ1代!jj人 明細書の「発明の詳細な説明」の掴 2 補止の内容 明細書の第6頁20行目から第7頁4行目にかけての[
そ、ρ分イスター器M・・・合理的稼動が行えることと
なる。]との記載を削除する。
Fig. 1 is an overall schematic diagram of a signal transmission system to which the present invention is applied, Fig. 2 is a block diagram showing the circuit configuration of a master device, Fig. 8 is a block diagram showing the circuit configuration of a transmitter, and Fig. 4 5 is a block diagram showing the circuit configuration of the receiver, and FIG. 5 is a format diagram of the transmission signal. M...Master device 'r1. T2...Tn...
Transmitters R,, R2...1. ...Receiver patent applicant Noboru Kono, agent of Tsubaki Chain Co., Ltd., patent attorney Figure 3! Figure 5 Procedures Amendment (Spontaneous) August 5, 1982 2 Title of the invention Signal transmission method 3 Relationship to the case of the person making the amendment Address of patent applicant 4-17-88 Tsurumi, Tsurumi-ku, Osaka City Name (335) Tsubaki Chain Co., Ltd. Representative Tomo Utsumi - Da 1 generation! How to understand the "detailed description of the invention" in the person's specification 2: [
So, the ρ minute Ister unit M... can be operated rationally. ] will be deleted.

Claims (1)

【特許請求の範囲】[Claims] 1、共通のラインに接続された被数の送、受信器間にて
信号ケ時分割的に伝送する方法において、送受信可能な
マスター器を設け、該マスター器は他の送信器が特定の
受信器に発した送信信号全受信1−1この受信信号に基
づきチェックサムコード全作成し、該チェックサムコー
ドをnfJ記受4d器へ送信するとさ全特徴とするイd
号伝送方法。
1. In a method of time-divisionally transmitting signals between transmitters and receivers connected to a common line, a master device capable of transmitting and receiving is provided, and the master device is used to enable other transmitters to receive specific signals. Receive all the transmitted signals sent to the device 1-1 Create a checksum code based on this received signal and send the checksum code to the NFJ recording device.
code transmission method.
JP10460983A 1983-06-10 1983-06-10 Signal transmitting method Pending JPS59229952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10460983A JPS59229952A (en) 1983-06-10 1983-06-10 Signal transmitting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10460983A JPS59229952A (en) 1983-06-10 1983-06-10 Signal transmitting method

Publications (1)

Publication Number Publication Date
JPS59229952A true JPS59229952A (en) 1984-12-24

Family

ID=14385166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10460983A Pending JPS59229952A (en) 1983-06-10 1983-06-10 Signal transmitting method

Country Status (1)

Country Link
JP (1) JPS59229952A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146842A (en) * 1974-10-18 1976-04-21 Matsushita Electric Ind Co Ltd
JPS53128204A (en) * 1977-04-14 1978-11-09 Fujitsu Ltd Connection system between different-type terminal units
JPS57168318A (en) * 1981-04-10 1982-10-16 Hitachi Ltd Data transmitting device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146842A (en) * 1974-10-18 1976-04-21 Matsushita Electric Ind Co Ltd
JPS53128204A (en) * 1977-04-14 1978-11-09 Fujitsu Ltd Connection system between different-type terminal units
JPS57168318A (en) * 1981-04-10 1982-10-16 Hitachi Ltd Data transmitting device

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