JPS59229831A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS59229831A
JPS59229831A JP58104198A JP10419883A JPS59229831A JP S59229831 A JPS59229831 A JP S59229831A JP 58104198 A JP58104198 A JP 58104198A JP 10419883 A JP10419883 A JP 10419883A JP S59229831 A JPS59229831 A JP S59229831A
Authority
JP
Japan
Prior art keywords
bonding
wire
semiconductor chip
area
welded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58104198A
Other languages
Japanese (ja)
Inventor
Kazuo Chihiro
和夫 千尋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP58104198A priority Critical patent/JPS59229831A/en
Publication of JPS59229831A publication Critical patent/JPS59229831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate the risk of short-circuit and improve integration density and welding intensity of wire providing a plurality of bonding areas between the other end of wire and electrode part of circuit substrate and giving the sequencial numbering to formation of bonding areas in the sequence from the further area from the semiconductor chip to the nearer area. CONSTITUTION:The one end 4a of wire 4 is welded to the bonding area 7 at the upper surface of semiconductor chip 1 and the other end 4b of wire 4 is welded to the first bonding area 9a at the furtherest area 10 from the semiconductor chip 1 on the electrode part 5. The second bonding area 9b is welded at the area a little nearer to the semiconductor chip 1 than the bonding area 9a. Moreover, the third bonding area 9c is welded at the area 11 more nearer to the semiconductor chip 1. In this way, a plurality of bonding areas are formed. When the wire 4 is pressed on the electrode part 5 by the end point of capillary 12 and thereby the second bonding area 9b is provided and is welded, the wire 4 extends in the longitudinal direction, but since the wire 4 cannot extend in the direction of bonding 9a due to the already provided bonding part 9a, it extends in the side of semiconductor chip 1.

Description

【発明の詳細な説明】 本発明は、半導体チップをワイヤにて回路基板の電極部
にボンディングして成る半導体装置、及びその製造方法
に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor chip is bonded to an electrode portion of a circuit board using a wire, and a method for manufacturing the same.

第１図は従来の半導体装置の断面図で、半導体チップｌ
を回路基板２にボンディングする場合、先づ回路基板２
の上にろう材３　（例えば金−シリコン共晶合金）で半
導体チップ１を固着し、核チップ１の上部にワイヤ４の
一端４ｇをボンディング部７にて固定し、回路基板２の
電極部５にワイヤ４の他端４ｂをボンディング部８にて
固定していセ。このボンディングには通常ウェッジボン
ディング等の手段が用匹られる。Figure 1 is a cross-sectional view of a conventional semiconductor device.
When bonding to the circuit board 2, first bond the circuit board 2.
The semiconductor chip 1 is fixed thereon with a brazing material 3 (for example, gold-silicon eutectic alloy), one end 4g of the wire 4 is fixed on the top of the core chip 1 with the bonding part 7, and the electrode part 5 of the circuit board 2 is fixed. The other end 4b of the wire 4 is fixed at the bonding part 8. For this bonding, means such as wedge bonding are usually used.

然し、第１図に示す如く、半導体チップ１の高さよりも
電極部５の高さが低い場合には、ワイヤ４がボンディン
グ部７からボンディング部８に向って下降するので、ボ
ンディングされたワイヤ４が半導体チップ１の角部６に
接触する危険があり、接触した場合は、ワイヤ４の断線
、ショートの原因となる。この危険を避けるために、電
極部５の高さを高くしてワイヤ４と半導体チップ１の角
部６との接触を避けるようＫすることも考えられるが、
そのためには、電極部５を特別なもので構成するか、又
は電極部５の上に別の電極を載せてがさ上げした上でボ
ンディングする必要があり、そのだめの工数増加や集積
度低下を来すため何れも良い解決策ではなかった。However, as shown in FIG. 1, when the height of the electrode section 5 is lower than the height of the semiconductor chip 1, the wire 4 descends from the bonding section 7 toward the bonding section 8, so that the bonded wire 4 There is a risk that the wires may come into contact with the corner portion 6 of the semiconductor chip 1, and if contact occurs, it may cause the wire 4 to be disconnected or short-circuited. In order to avoid this risk, it may be possible to increase the height of the electrode section 5 to avoid contact between the wire 4 and the corner section 6 of the semiconductor chip 1;
To do this, it is necessary to construct the electrode part 5 with a special material, or to place another electrode on top of the electrode part 5 and raise it up before bonding, which increases the number of man-hours and reduces the degree of integration. None of these were good solutions.

本発明は、上記従来の欠点を改良せんとするものであり
、本発明の目的は、ワイヤが半導体チップの角部に当る
ことがなく、集積度が高く、且つワイヤの圧着強度が高
り半導体装置及びそのワイヤのボンディング方法を提供
せんとするものである。第２図〜第３図は何れも本発明
の実施例を示し、第２図は半導体装置の断面図、第３色
は第２図に示す半導体装置を製造する製造方法を説明す
るための断面図である。なお、第１図の従来例と同一部
分は同一番号を付して詳細な説明は省略する。The present invention aims to improve the above-mentioned conventional drawbacks, and an object of the present invention is to prevent the wires from touching the corners of the semiconductor chip, achieve a high degree of integration, and increase the crimp strength of the wires. It is an object of the present invention to provide a device and a method for bonding its wires. 2 to 3 each show an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor device, and the third color is a cross-sectional view for explaining the manufacturing method for manufacturing the semiconductor device shown in FIG. It is a diagram. Note that the same parts as in the conventional example shown in FIG. 1 are given the same numbers and detailed explanations are omitted.

従来例と本発明の相異点は、ワイヤの他端と回路基板の
電極部とのボンディング部を複数劇所設け、且つ各ボン
ディング部の形成順序を、半導体チップより遠い箇所か
ら順次近Ａ箇所へと順序付けた点である。The difference between the conventional example and the present invention is that a plurality of bonding portions are provided between the other end of the wire and the electrode portion of the circuit board, and the formation order of each bonding portion is sequentially changed from a point farthest from the semiconductor chip to a near point A. This is the order of points.

これを詳述すれば、ワイヤ４の一端４ａ’（ｉ−半導体
チップ１の上面にボンディング部７で固着し、ワイヤ４
の他端４ｂを電極部５上の半導体チップ１から最も遠い
箇所１０に於て第１のボンディング部９ａで固着する。To explain this in detail, one end 4a' of the wire 4 (i- is fixed to the upper surface of the semiconductor chip 1 by the bonding part 7,
The other end 4b is fixed at a point 10 on the electrode section 5 farthest from the semiconductor chip 1 with a first bonding section 9a.

次に前記ボンディング部９ａより少し半導体チップ１側
に近い箇所に於て第２のボンディング部９ｂで固着する
。次に更に半導体チップ１に近い箇所１１に於て第３の
ボンディング部９ｃで固着する。以下このように繰返し
複数のボンディング部を形成する。Next, it is fixed with a second bonding part 9b at a location slightly closer to the semiconductor chip 1 side than the bonding part 9a. Next, a third bonding portion 9c is used to fix the semiconductor chip 1 at a location 11 close to the semiconductor chip 1. Thereafter, a plurality of bonding portions are repeatedly formed in this manner.

今例えば、ボンディング部ｅ９ａ、９ｂ、９ｃと３ヶ設
けた場合につき説明する一第３図に示す如く第１のボン
ディング部９ａ？設けた後、ワイヤ４をキャピラリ１２
の先端によって電極部５上におしつぶして第２のボンデ
ィング部９ｂを設けて固着すると、ワイヤ４はその長さ
方向に延びるが、この時、既に設けられたボンディング
部９ａによって、ワイヤ４はボンディング部９ａ方向に
は延びることが出来ないので、必然的に半導体チップ１
側に延びる。一方、ワイヤ４の一端４ａもボンディング
部７にて既に固着されているので、ワイヤ４は結局第３
図矢印Ａ％Ｂ方向に延びて湾曲し、半導体チップ１０角
部６から離れる形となる。次に、第３のボンディング部
９ｃｉ設ける時も同様である。For example, a case will be described in which three bonding parts e9a, 9b, and 9c are provided.As shown in FIG. 3, the first bonding part 9a? After installing the wire 4, connect it to the capillary 12.
When the tip of the wire 4 is crushed onto the electrode part 5 to provide a second bonding part 9b and fixed, the wire 4 extends in its length direction, but at this time, the wire 4 is Since it cannot extend in the direction of the bonding portion 9a, it is inevitable that the semiconductor chip 1
extends to the side. On the other hand, since one end 4a of the wire 4 is also already fixed at the bonding part 7, the wire 4 ends up in the third
It is curved and extends in the direction of arrow A%B in the figure, and is separated from the corner 6 of the semiconductor chip 10. Next, the same applies when providing the third bonding portion 9ci.

本発明によれば、上述せる如く、ワイヤは半導体素子の
角部に触れることがなｈ様に出来るから、断線、ショー
トの危険はなく、また従来の欠点であった電極部の高さ
を高くする必要もなりので、集積度を従来に比し増すこ
とが出来、且つボンディング部が複数箇所設けられるの
で、ワイヤの固着強度カ；増すという効果を有する。According to the present invention, as mentioned above, the wire can be made in such a way that it does not touch the corner of the semiconductor element, so there is no risk of disconnection or short circuit, and the height of the electrode part, which was a drawback of the conventional method, can be increased. Since there is no need to do this, the degree of integration can be increased compared to the conventional method, and since a plurality of bonding parts are provided, it has the effect of increasing the strength of bonding the wire.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の断面図、第２図、第３図は
本発明の一実施例を示し、第２図は半導体装置の断面口
、第３図は第２図に示す半導体装置を製造する製造方法
を説明するだめの断面図である。 １・・・・・・半導体チップ、２・・・・・・回路基板
、３・・・・・・ろう材、４・・・・・・ワイヤ、５・
・・・・・電極部、６・・・・・・角部、７，８，９ａ
、９ｂ、９ｃ・・・・・・ボンディング部、ｌＯ・・・
・・・最も遠い箇所、１１・・・・・・近い箇所。FIG. 1 is a cross-sectional view of a conventional semiconductor device, FIGS. 2 and 3 show an embodiment of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device, and FIG. 3 is a semiconductor device shown in FIG. FIG. 1... Semiconductor chip, 2... Circuit board, 3... Brazing material, 4... Wire, 5...
... Electrode part, 6 ... Corner part, 7, 8, 9a
, 9b, 9c... bonding part, lO...
...farthest point, 11...closest point.

Claims (1)

【特許請求の範囲】 α）半導体チップに一方の端部がボンディングされたワ
イヤの他端を回路基板の電極にボンディングした半導体
装置に於て、前記他端に複数のボンディング部を形成し
たことを特徴とする半導体装置。 （２）半導体チップに一方の端部がボンディングされた
ワイヤの他端を回路基板の電極にボンディングし、前記
他端に複数のボンディング部を形成した半導体装置を製
造する方法に於て、前記ボンディング部を、前記半導体
チップから最も遠い箇所から順次近い箇所に向って形成
することを特徴とする半導体装置の製造方法。[Claims] α) In a semiconductor device in which one end of a wire is bonded to a semiconductor chip and the other end is bonded to an electrode of a circuit board, a plurality of bonding portions are formed at the other end. Characteristic semiconductor devices. (2) In a method for manufacturing a semiconductor device in which one end of a wire is bonded to a semiconductor chip and the other end is bonded to an electrode of a circuit board, and a plurality of bonding parts are formed at the other end, the bonding A method of manufacturing a semiconductor device, characterized in that the portions are formed sequentially from a location farthest from the semiconductor chip to a location close to the semiconductor chip.
JP58104198A 1983-06-13 1983-06-13 Semiconductor device and manufacture thereof Pending JPS59229831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58104198A JPS59229831A (en) 1983-06-13 1983-06-13 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58104198A JPS59229831A (en) 1983-06-13 1983-06-13 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS59229831A true JPS59229831A (en) 1984-12-24

Family

ID=14374275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58104198A Pending JPS59229831A (en) 1983-06-13 1983-06-13 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS59229831A (en)

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