JPS59229687A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify the packaging of the titled device, to improve the reliability of operation and to increase the degree of integration by connecting two terminals ech of which is to be used as a power supply input and a signal I/O to an external device. CONSTITUTION:When transmission data S4 are to be sent from the external device 20 to an IC chip 10, a variable resistor RS is ''0'', i.e. shorted, and square wave voltage of ISRL is impressed to the input of a sensing amplifier A2 as peak-to-peak and the amplified voltage is taken out as received data S3. When the transmission data S4 are to be transmitted from the IC chip 10 to the external device 20, variable current IS is turned to ''0'', so that the square wave voltage of IORS is impressed to the input of a sensing amplifier A1 and the amplified voltage is taken out the as received data S3.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a two-terminal integrated circuit device.

[Technical background of the invention and its problems]

Due to remarkable advances in semiconductor integrated circuit technology and packaging technology in recent years, integrated circuit chips (hereinafter referred to as C-chips) with information processing functions have been added to Noraste cards, similar to credit cards, cash cards, etc., which have been widely used in the past. In other words, a so-called IC card equipped with a relatively simple CPU and memory has been developed and is reaching a practical stage.

The first @ shows an example of the configuration of an IC card such as the one shown in the figure, in which a plastic card-like base 1 has a magnetic stripe (not shown) to ensure compatibility with conventional magnetic cards such as credit cards. ) and IC area 2 are configured. As shown in the enlarged cross section of FIG. 1(b), the IC area 2 has an IC tip 5 on the inner surface of a support plate 4 fixed to a recess formed in the card-like base 1 via a sweep 3.
The terminals (tending pads) of this IC tip 5 are connected via lead wires 6 to about 5 to 8 electrodes 7 formed on the support plate 4, and the IC tips are connected through these electrodes 7. 5 and an external device such as an IC card reader.

However, with such a structure l) IC chip 5
Since a space is required to take out the lead wire 6 from the upper terminal, there are problems in that it is difficult to reduce the thickness of the card and dust is generated, and the mounting process is complicated because it includes wire ending. Furthermore, another drawback is that it is difficult to ensure the reliability of the connections between the large number of electrodes 7 and external devices.

[Purpose of the invention]

An object of the present invention is to provide an integrated circuit device that has a small number of external connection terminals and can be easily attached to a flat object such as an IC card.

[Summary of the invention]

The integrated circuit device according to the present invention includes two terminals serving as power input and signal input/output as terminals for connection with an external device, and furthermore, signals are supplied from the external device through these terminals. a signal detection means for detecting a signal superimposed on a power supply input; a signal sending means for sending a signal to be transmitted to an external device to the terminal; and a signal detection means for processing the signal detected by the signal detection means; The present invention is characterized by comprising a signal processing means for generating a signal to be sent out from the signal sending means.

〔Effect of the invention〕

According to this invention, since the number of external connection terminals is only two,
For example, these terminals are connected to integrated circuit chips.

If these terminals are formed on the front and back sides of an IC card, etc., and then mounted so that these terminals are located on the front and back sides of an IC card, etc., it is possible to use the conventional IJ-wires. This eliminates the need for space for loading, and can contribute to making IC cards and the like thinner. In addition, since complicated wire bonding is not required, mounting is simple and the number of man-hours can be significantly reduced.

Furthermore, since a large current due to power input in addition to the signal current flows through the terminals, a cleaning effect on the terminals can be expected and the reliability of operation can be improved.

Furthermore, by reducing the number of terminals, it is possible to increase the number of internal elements and the degree of integration of an integrated circuit chip, so if the chip size remains the same, the information processing capacity (for example, memory capacity, etc.) can be increased. In addition, if the information processing capacity remains the same, the chip size can be made much smaller.

[Embodiments of the invention]

2(a) and 2(b) show the principle of the circuit configuration of an integrated circuit device 10 (hereinafter referred to as an IC chip) according to the present invention and an external device 20 connected thereto, and (a) shows the voltage An example of a drive type, (b) is an example of a current drive type.

In FIG. 2(,), an external device 20 is an IC chip 10.
a DC voltage source vo for supplying power to the DC voltage source, a variable voltage source v8 whose voltage changes to two values of 0 and vs in response to the transmission data signal S1, a resistor r for current change detection, and a DC voltage source v8 for supplying power to the Capacitor C1 for component blocking and received data signal S
2, and a sense amplifier A1 that obtains a value of 2.

On the other hand, the IC chip 10 includes a load circuit RL including a CPU, memory, etc., a level shift circuit LS for blocking a DC component to detect changes in current flowing into the RL, a sense amplifier fA2 for obtaining a received data signal S3, and a sense amplifier fA2 for obtaining a received data signal S3, and a sense amplifier fA2 for obtaining a received data signal S3. It consists of a variable resistor R whose resistance value changes to two values, R8 and R8, in response to a signal S4, and is connected to an external device 20 via terminals 11 and 12.

Now, let us consider the case where the transmission data signal Sl is sent from the external device 20 to the fiIc unit 7''zo. In this state, the value of the variable resistor R8 is set to ■, and the input of the sense amplifier fA is peak-to-peak. Peeling (RL + r) vs.
A square wave voltage is applied, which is amplified and taken out as a received data signal Sj. Note that r represents the resistance value of the resistor r, and RL represents the equal-side internal resistance of the load circuit RL. On the other hand, conversely, data S is transmitted from the IC step 10 to the external device 2o.
4 is sent, the voltage of the variable voltage source v8 is set to O, and a peak-to-peak square wave voltage is applied to the input of the sense amplifier fAl, which is amplified and taken out as the received data signal S2. Ru. vo represents the voltage of the DC voltage source vo. Note that the equal-side internal resistance RL of the load circuit RL
It is assumed that the value is approximately constant regardless of the internal state of the IC chip 1o.

By the way, RL = 100 Q, r = 100. Q, R8
= 5750, VB = 0.4V, VO = 5V, the input voltage of sense amplifier 7''A1 and A2 is both 0.2
vIMp9 is a voltage that can be sufficiently detected by the sense amplifier.

On the other hand, according to the current side dynamic configuration shown in FIG. 2(b), the external device 20 is a current source 1. , the currents O and I correspond to the transmission data signal S1.
It consists of a variable current source 6 that changes into two values (s and s), a capacitor C1 for blocking a DC component, and a sense amplifier A1 for detecting voltage changes. Also, Engineering C Tezzo 1
0 consists of a load circuit RL and a variable resistor RS whose resistance value changes to two values, 0 and R8, in response to a voltage change signal S4 applied to the load circuit RL.

Now, data Sl is sent from the external device 20 to the IC chip 10.
is sent, variable resistor R8 is set to R8=0, that is, short-circuited, and a square wave voltage of 18RL is applied peak-to-peak to the input of sense amplifier A2, and this is amplified to output the received data. It is extracted as S3. On the other hand, when the transmission data S4 is sent from the IC test fl (7) to the external device 2o, the current of the variable current s is set to 0, and the input of the sense amplifier fA1 becomes ■oR8 peak-to-peak. A square wave voltage is applied, which is amplified and extracted as received data S3.RL
= 1008, R8-80, Io=25mA, IB==
If the input voltage is 2 mA, the input voltage of the sense antenna 7°AI, ''2 will be 0.2 VppJ, which is a sufficiently detectable voltage.

In the above explanation, the equal-side internal resistance RL of the load circuit RL is assumed to be almost constant; however, in reality, it changes with changes in its internal operating state, and this change causes an error voltage to be applied to the input of the sense antenna A2. This results in a decrease in S and may cause malfunction.

Assuming that S is maintained at 10 dB or more, the change in resistance RL near the frequency of the transmitted/received data signal or higher is shown in Figure 2 (
The voltage-driven configuration (a) allows up to ±30%, and the current-driven configuration (b) allows up to 2.5%. This is advantageous in terms of H.

As a measure to suppress the fluctuation of the input voltage of the sense amplifier A2 due to the resistance change (load fluctuation) of the load circuit RL to below the permissible value, for example, the method shown in FIG. 3(a) is used.

As shown in (b), there is a method of adding a dummy resistor RD in series or parallel to the load circuit RL to reduce the influence of fluctuations in R. In addition, by further developing Fig. 3(,) and (b), the fluctuation of RL is detected by the control circuit C0NT as shown in Fig. 3(c) and (d), and the dummy resistor RDO is set accordingly. It would be more effective to control the load to a constant value near the maximum load when the load is always performing its original function by changing the load.

Another method is to use a load circuit RL itself that has little load fluctuation due to state changes, or to perform only simple operations with small load fluctuations (such as buffer memory write and read operations) when transmitting and receiving data signals. It is also effective to carry out other complicated operations that involve large load fluctuations in a state other than transmission/reception.

Although there is a so-called ping-pong transmission that does not occur at the same time, for example, as shown in Fig. 4, there is a method to cancel the data signal transmitted from the own device (IC Chisso 10 or external device 20) before the sense amplifier A. By inserting a hybrid circuit Hyb, it is also possible to perform bidirectional simultaneous transmission.

FIG. 5 shows more specifically the voltage-driven configuration of FIG. 2(a), in which a switching transistor (in the illustrated example, a MOSFET) 701 and a resistor 102 are variable resistors R.

The level shift circuit 103 is a level shift circuit (LS
The resistor 104 and the connogrator 105 respectively correspond to the sense amplifier A2, and the stabilized power supply 10G and the synchronous oscillator 107, encoder 108, decoder 109, controller, and memory 110 that receive power therefrom are connected to the load circuit RL. Compatible. On the other hand, in the external device 20, a power supply 201 is connected to a voltage source Vo, and a resistor 2
02 is the resistor r, the driver 203 and the capacitor 20
4 corresponds to a variable voltage source 8, a capacitor 205 corresponds to a coil capacitor C1, and a resistor 206 and a comparator 207 to a hasens amplifier A1.

Now, in the above configuration, the IC chip fxo and the external device 2
As shown in Fig. 6, the data signal sent to and from data signal, and if necessary, an error correction code such as CRC is added after the data signal. These signals are converted into a code on which a clock signal is superimposed, for example, a Manchester code as shown in FIG.

The above-mentioned preamble signal etc. are added to another circuit in the external device 20, and the transmitted data signal S is further encoded.
l is applied to the converter 105 and the synchronous oscillator 107 via the driver 2θ3 capacitor 204 and the IC chip. A synchronizing signal oscillator 107, which is equipped with a circuit for extracting a cyclic signal from the encoded signal described above, generates a clock signal of a higher frequency in synchronization with the extracted clock signal, an encoder 108, a decoder 109, a controller, and a memory. 110.

On the other hand, the signal detected through level shift circuit 103, shaped and amplified by comparator 10F is decoded by decoder 109, and sent to controller and memory 110 as received data signal S3. On the contrary, I
When transmitting the transmission data signal S4 from the C chip 10 to the external device 20, the controller and memory 110 receive the clock signal from the synchronous oscillator 107, which is in a free running state, and send the transmission data to which a preamble signal etc. have been added. After a signal is generated and further encoded by the encoder 108, the encoded signal causes the transistor 1 to
01 is turned ON/OFF, the resistor 102
The current flowing through the circuit is controlled. This current change occurs at terminal 11.
12 to an external device 20, and the capacitor 20
5, is detected and amplified by a resistor 206 and a converter 207, and then supplied to another circuit within the external device 20. Also, from the external device 20, there is a terminal 11 inside the IC chip 10.
．． The DC power supplied through the terminal 12 is converted by the stabilized power supply 106 into a voltage vDD which is lower than the average voltage ■T of the terminal 11, as shown in FIG. .

The stabilized power supply 106 includes a dummy resistor for keeping the equal-side internal resistance described above substantially constant, and a control circuit if necessary. The level shift circuit 103 for removing DC components is preferably one that utilizes the VBE of a transistor or the forward voltage drop of a diode, but since the input resistance of the comparator 105 is extremely large, a capacitor of small capacity is used. It is possible to pass a desired band signal even if there are two types, and in either case, it can be configured in a monolithic IC.

FIG. 8 shows another configuration example of the IC chip 1o, in which the transistor 101 and resistor 102 in FIG. 5 are replaced with a driver 111, and the output end of the driver 111 is connected to the first Connected to terminal 11. In addition, the level shift circuit 103, resistor 104, and comparator 105 in FIG.
and capacitor 115, and synchronous oscillator 107 is replaced by oscillator 116, respectively. As shown in FIG. 9, the data signal to be transmitted and received is encoded into, for example, a die-cut code, and the decoder 109 performs self-oscillation and decoding, and outputs the received data signal s3. do. Similarly, the transmitted data signal s4 from the controller and memory 110 is encoded into a clock signal from the oscillator 116 by an encoder, amplified by a driver 111 having an appropriate output impedance, and then connected to a capacitor 112. AC coupling is made to the first terminal 11 via the first terminal 11 . On the other hand, the output of the boost stabilized power supply 114 is
The voltage is boosted and stabilized to be the same voltage as the average level T of the diphase code shown in the figure, and is used as a reference voltage for the comparator 1130. Therefore, the signal input terminal of the comparator 113 is connected to the first terminal 1 without going through the DC component blocking level shift circuit 103 as shown in FIG.
It is directly connected to 1. Note that in this embodiment, capacitor 1
Since a relatively large capacitance is required as 12.115, a hybrid configuration using a chip capacitor or the like is required at the current technological level.

Further, in the above explanation, the data signal is transmitted as it is in the base band, but it goes without saying that the data signal may be converted into a modulated wave such as FM, AM, PM, etc. and then superimposed on the DC power. In particular, when modulating the carrier wave, if the carrier wave is selected to be a high frequency wave such as a short wave or a very short wave, the capacitors 112, 115, etc. need only have small capacitance, and can be easily formed in an IC chip.

FIGS. 10(a) and 10(b) show an example of the arrangement structure of the terminals 11 and 12 when the IC chip 1o is monolithically constructed. An insulating layer or IE made of 5i02, polyimide, silicon nitride, etc. is formed on the wiring 14, and the first terminal 11 is deposited thereon by vapor deposition or the like.
The second terminal 12 is formed by vapor deposition on the reverse side of No. 3. Here, the second terminal 12 serves as a ground terminal, and in the example (-), it is internally connected to the ground wiring 14' on the board 13, and in the example (b), it is connected to the conductive wire on the side surface of the board 13. It is connected to the ground wire 14' by a conductive adhesive material 16 such as epoxy resin, for example silver paste.

FIG. 11 shows an example in which the present invention is applied to an IC card. In FIG. 11(,), the IC chip 10
are held by two card-like bases 21a and 21b made of an insulating material such as plastic, and the terminals 11.
12 are connected to electrodes 22 and 23 formed on the card-like substrates 21m and 21b, respectively. That is, the card-like substrates 21a and 21b have a through hole in the IC area whose diameter changes in two steps, and the IC chip 10 is bonded with an adhesive with the large diameter portions of the holes facing each other.
Clamp and fix.

The electrodes 22,23 are in this case card-like substrates 21a.

The small diameter portion of the through hole of 21b is made of a conductive material such as conductive epoxy resin, and the terminal 1 of the IC chip fxo is made of a conductive material such as a conductive epoxy resin.
1.12 and an external device described later.

In FIG. 11(b), electrodes 22, 23 are formed on the entire front and back surfaces of the card-like substrate 21, and are connected to the IC chips 7'' by conductive members 24, 25 having flexibility such as conductive rubber.
10 terminals 11.12.

In FIG. 11(C), the electrodes 22.degree. 23 and the terminals 11.12 are connected using spring contacts 26, 27 instead of the conductive rubber or the like in FIG. 11(b).

FIG. 11(d) shows a protrusion 22a on the inner surface of the electrode 22.23,
23a is integrally formed, the IC chip 1o is sandwiched between the protrusions 22m and 23a, and the electrodes 22.23 and the terminals 11.1 are connected.
It is designed to make a connection with 2.

FIG. 11(e) is the same as that of FIG. 11(b) except that electrodes 22 and 23 are provided on a part of the card-like base 21.

FIG. 11(f) shows an example in which the electrodes 22 and 23 are made of a flexible conductive member such as conductive rubber or conductive plastic and are directly connected to the terminals 11 and 12 of the IC chip 1o. In this case, if the card-like base 2 is also made of a flexible material such as soft rubber, the IC card as a whole will be flexible.

By the way, in the circuit configuration of FIG. 5 or 8, the IC
If the card is inserted into the external device 2o with the front and back reversed, there is a risk that current will flow in the opposite direction and damage the circuit inside the ICC tablet 10. FIG. 12 shows an embodiment in which an IC card can be inserted upside down. A diode I is connected to the first terminal 11 of the IC chip 10, and the IC chip 1θ is connected to the IC chip 1θ through this diode. DC power and data signals are supplied to each circuit within the circuit. With this configuration, even if the IC card is inserted into the external device 20 upside down, the circuit will not be destroyed, and furthermore, when the IC card is inserted into the external device 20 side, the IC chip 1
If the current flowing into the IC chip 10 is detected and an appropriate current is flowing, data signal transmission is started as is. Conversely, if an appropriate current is not flowing, the IC chip 10 is It is also possible to automatically switch the direction of connection with the terminals 11 and 12 to be reversed and to start data signal transmission after confirming that a proper current has started flowing.

FIG. 13 shows an example in which the IC chip 10 having such a configuration is applied to a so-called electronic coin. 11.12 to electrode J2:',
It is connected to 23. Such coins can be used in vending machines, etc., just like normal coins, without having to be aware of the front or back sides.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a side view and an enlarged sectional view of the main parts of a conventional IC card, and FIGS. 2(a) and (b) are voltage-driven and Equivalent circuit diagrams of a current-driven integrated circuit device and an external device connected to it; FIGS. 3(a) to (d) are diagrams for explaining a method of compensating for fluctuations in equal-side internal resistance of a load circuit using dummy resistors; FIG. 4 is a diagram showing the configuration of a device for simultaneous bidirectional transmission, FIG. 5 is a circuit diagram showing the configuration of an integrated circuit device according to an embodiment of the present invention together with external devices, and FIG. 7 is a diagram showing an example of Manchester encoding a data signal, FIG. 8 is a circuit diagram showing another embodiment of the present invention, and FIG. 9 is a diagram showing the die phase of the data signal in the same embodiment. A diagram showing an example of encoding, Fig. 10 (
a) and (b) are cross-sectional views showing the TEG structure of the integrated circuit device according to the present invention, and Figures 11 (,) to (f) are cross-sectional views showing an example in which the integrated circuit device according to the present invention is mounted on an IC card. Figure 12 is a diagram showing a part of the circuit configuration of an integrated circuit device useful for an IC card that can be inserted upside down.
3(a) and 3(b) are a plan view and a sectional view showing an example in which the present invention is applied to an electronic coin. 10...IC chip (integrated circuit device), 11°12.
...terminal, 20...external device, 101, 102°11
1.112...Signal sending means, 103,104°10
5.113...Signal detection means, IO8, 109°11
0...Signal processing means. Applicant's representative Patent attorney Takehiko Suzue No. 9wJ No. 10m 2 (b) Figure 11 Figure 12 Figure 13 (a) (b)

Claims (1)

[Claims] (1) Two terminals for connection with an external device, and signal detection for detecting a signal superimposed on the power input supplied from the external device through these terminals. a signal transmitting means for transmitting a signal to be transmitted to the external device to the terminal; and a signal processing means for processing the signal detected by the signal detecting means and generating a signal to be transmitted from the signal transmitting means. An integrated circuit device comprising: (2) The signal detecting means, the signal sending means, and the signal processing means are constructed in one integrated circuit chip, and the terminals are formed on both the front and back surfaces of the integrated circuit chip. The integrated circuit device according to scope 1. (3) The integrated circuit device 0 according to claim 1, wherein signal transmission and reception with an external device and power supply from the external device are performed via a diode connected to the terminal. (4) Claims characterized in that the integrated circuit chip includes a dummy resistor to keep the power consumption of the circuit portions other than the final stage of the signal sending means substantially constant regardless of changes in its internal operating state. The integrated circuit device according to item 2. (5) The integrated circuit device 0 according to claim 4, wherein the dummy resistor is a variable resistor. (6) The integrated circuit step performs limited operation with less load fluctuation when transmitting and receiving signals. The integrated circuit device according to claim 2 or 4, characterized in that the integrated circuit device performs only the following. (7) The signal detection means 2 includes a level shift circuit for DC component blocking, one end of which is connected to either one of the two terminals, and a sense amplifier, whose input end is connected to the other end of this level shift circuit. An integrated recall device as claimed in claim 1 or 2, characterized in that it comprises the following. (8) Claim 7, characterized in that the sense amplifier is a comparator in which the other end of a level shift circuit for removing DC components is connected to one input end and a constant potential is applied to the other input end. The integrated circuit device described in Section 1. (9) The signal sending means includes a variable resistance element connected between the two terminals, and the resistance value of the variable resistance element is controlled in accordance with the signal to be transmitted to an external device. An integrated circuit device according to claim 1 or 2. The αQ signal detection means is characterized in that it includes a comparator, one input end of which is connected to one of the two terminals, and the other input end of which is supplied with a voltage obtained by boosting and stabilizing the power input supplied from an external device. An integrated circuit device according to claim 1 or 2. CLI) The signal sending means includes a driver that amplifies the signal to be transmitted to an external device, an output end of this driver, and the above-mentioned 2.
3. The integrated circuit device according to claim 1, further comprising a capacitor for AC coupling connected between one of the terminals of the integrated circuit device.