JPS59227120A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59227120A
JPS59227120A JP10190583A JP10190583A JPS59227120A JP S59227120 A JPS59227120 A JP S59227120A JP 10190583 A JP10190583 A JP 10190583A JP 10190583 A JP10190583 A JP 10190583A JP S59227120 A JPS59227120 A JP S59227120A
Authority
JP
Japan
Prior art keywords
layer
schottky
metal
mask
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10190583A
Other languages
Japanese (ja)
Inventor
Reiji Takashina
高階 礼児
Masakazu Ishino
石野 雅一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10190583A priority Critical patent/JPS59227120A/en
Publication of JPS59227120A publication Critical patent/JPS59227120A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the disconnection of a wiring electrode due to a difference in level and the discoloration of a metal on a Schottky metal layer, by using a metal layer or an Schottky metal as a mask when the Schottky metal is etched. CONSTITUTION:A buried region 2, an epitaxial layer 3, an oxide film layer 4, an ohmic diffusion region 11, a Schottky window and a Ti layer 5 formig a Schottky layer are formed on a semiconductor substrate 1, and then an Mo layer 6 is evaporated thereon. Next, the entire surface is covered with a photo resist 7, and thereafter the resist 7 is removed except for the part thereof covering the Schottky window, so as to expose a part of the layer 6. Then, the remaining resist 7 being used as a mask, the layer 6 is removed by etching to expose the layer 5. After the resist 7 is removed, the layer 5 is removed by etching with the layer 6 used as a mask. After a part of the surface of the ohmic diffusion layer is exposed thereafter, a Schottky electrode 8 and an manufacture, a part to which metal sticks again can be reduced sharply, and as the result, a defect of wiring electrodes due to a difference in level, as well as the discoloration of the layer 6, can be eliminated.

Description

【発明の詳細な説明】 本発明杜ショットキー障壁を有する半導体装置に関しζ
特にオーミック電極とが同一平面上に形成された半導体
装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a Schottky barrier.
In particular, the present invention relates to a method of manufacturing a semiconductor device in which an ohmic electrode is formed on the same plane.

近年、UHF、V)Ili’i装置ノI C(l伴イ、
複数個のダイオードモノリシック集積化するのに便利な
構造としてオーミック電極とショットキー電極とを同一
平面上に形成した。いわゆる横形のダイオード構造が扮
案されている。この構造をもつダイオードの直列抵抗は
、ショットキー゛的捧からオーミック電極への広がり抵
抗が主となシ、電極間隔が短かくかつショットキー電極
の周囲長が長いものほど小さくなるという%徴がある。
In recent years, UHF, V) Ili'i equipment,
An ohmic electrode and a Schottky electrode are formed on the same plane as a convenient structure for monolithically integrating a plurality of diodes. A so-called horizontal diode structure has been proposed. The series resistance of a diode with this structure is mainly due to the spread resistance from the Schottky effect to the ohmic electrode, and there is a % characteristic that the shorter the electrode interval and the longer the circumference of the Schottky electrode, the smaller the resistance. be.

仁のような構造を作成する技術としてね、卯1図に平面
図を示すように半導体動作層に矩形状に接触する複数の
オーミック亀1&と、これらオーミック電極間に位置し
半導体動作層に矩形状に接触するショットキー電極とを
備えた矩形ショットイ・−ダイオードがある。かかる構
造のショットキーダイオードを得るための一般的なkl
’llt方法をu52図〜第5図に示す。
As shown in the plan view in Figure 1, the technology for creating a 2-layer structure is as follows. There is a rectangular Schottky diode with a Schottky electrode contacting the shape. General kl to obtain a Schottky diode with such structure
The 'llt method is shown in Figures u52 to Figure 5.

まず半導体基板1に半導体基板1と反対の導11(1型
を呈する埋込領域2を形成した後、通當の気相成長法に
よシ半導体基板1と反対の導籐型に呈ゴるエピタキシャ
ル層3を形成する。次に酸化M’p )t34を形成し
た後、通常の写真蝕刻法によシ酸化膜層4の一部、すな
わちオーミック領域に相当する部分をエツチング除去し
、エピタキシャル層3を露出させた後(第2図)、埋込
領域と同じ導電型を呈する不納物を高濃度に拡散してオ
ーミック領域11を形成する。
First, a buried region 2 having a conductive type 11 (type 1) opposite to that of the semiconductor substrate 1 is formed on a semiconductor substrate 1, and then it is formed into a conductive type opposite to that of the semiconductor substrate 1 by a conventional vapor phase growth method. An epitaxial layer 3 is formed. Next, after forming an oxide M'p)t34, a part of the oxide film layer 4, that is, a part corresponding to the ohmic region, is etched away by ordinary photolithography, and the epitaxial layer 3 is formed. After exposing 3 (FIG. 2), an ohmic region 11 is formed by diffusing an impurity having the same conductivity type as the buried region at a high concentration.

次に熱酸化してオーミック領域を酸化膜4で覆った後、
さらに酸化膜層4の一部すなわちショットキー領式に相
当する部分をエツチング除去し、エピタキシャルff1
3を露出させてシロットキー窓を開孔する。次に100
OAのチタン層5及び同じ(1000λのモリブデン層
6を連続蒸着した後、全面を7オトレジストフで覆う。
Next, after thermal oxidation and covering the ohmic region with an oxide film 4,
Further, a part of the oxide film layer 4, that is, a part corresponding to the Schottky region, is removed by etching, and the epitaxial layer ff1 is etched away.
3 is exposed and the sirot key window is drilled. then 100
After successive evaporation of a titanium layer 5 of OA and a molybdenum layer 6 of the same (1000λ), the entire surface is covered with 7 photoresists.

しかる後、通常の写真蝕刻法によショットキー特性り外
のフォトレジストを除去し、前記モリブデン層6を露出
させる。次に7オトレジストをマスクとして通常のイオ
ンミリング法によ)露出させたモリブデン層6及びチタ
ン層5を除去する(第4図)。次にフォトレジストを除
去した後、オーミック′rl極取シ出し部上の酸化膜を
除去して表面を露出させ、電極と分る金属を蒸着してオ
ーミック電析9とシ1ットキーW、i8とを形成する(
第5図)。
Thereafter, the photoresist having non-Schottky characteristics is removed by ordinary photolithography to expose the molybdenum layer 6. Next, the exposed molybdenum layer 6 and titanium layer 5 are removed by a conventional ion milling method using the photoresist 7 as a mask (FIG. 4). Next, after removing the photoresist, the oxide film on the ohmic 'rl electrode extraction part is removed to expose the surface, and a metal that can be used as an electrode is vapor deposited to form the ohmic electrode 9 and the sheet key W, i8. and form (
Figure 5).

かかる製法においては、は#ワ:1司じ厚てで形hl・
されたチタン層5及びモリブデン1φ6をイオンミリン
グ法によシエッチング診去するときのマスクとしてフォ
トレジストを用いているため、エツチング側面が厚くメ
タル再付着層10が7オトレジストの部分にまで形成さ
れる。その結果、この再付着層が良好に除去できずにそ
のため、アルミ111枦を形成するときに段切れをしば
しば発生し、オープン不声及び信頼度低下のa1固とな
っていた。さらに又、イオンミリングのマスクとして用
いたフォトレジストを除去するためには、酸化プラズマ
を照射しガければならないが、その時に下層の金IFM
Cモリプラン層)6が馴化されて誓合するという現象が
しばしば発生し、■F不良及びショットキー特性の劣化
等という間かを引き起こし、ていた。
In such a manufacturing method, the shape is HL with a thickness of 1.
Since a photoresist is used as a mask when etching away the etched titanium layer 5 and molybdenum 1φ6 by ion milling, the etched side surface is thick and the metal re-deposition layer 10 is formed up to the photoresist part 7. . As a result, this redeposited layer could not be removed satisfactorily, and as a result, step breakage often occurred when forming the aluminum 111 frame, resulting in open noise and poor reliability. Furthermore, in order to remove the photoresist used as a mask for ion milling, oxidation plasma must be irradiated, but at that time the underlying gold IFM
A phenomenon in which the C Moriplan layer) 6 becomes acclimatized and forms a bond often occurs, causing problems such as ①F defects and deterioration of Schottky characteristics.

本発明は電極の段切れ及びシロットキー金属層上の金属
の変色をなくした新規な半導体装置の製造方法を提供す
るものである。
The present invention provides a novel method for manufacturing a semiconductor device that eliminates step-breaks in electrodes and discoloration of metal on a white-key metal layer.

以下1本発明の一実施例につき図面を参照しながら詳細
に説明する。第6〜8図は本発明の一実施例を示す各製
造工程断面図である。従来と同一の部分は、同一番号を
付している。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. 6 to 8 are sectional views of each manufacturing process showing an embodiment of the present invention. The same parts as before are given the same numbers.

従来製法と同様にして、半導体基板1に埋込領域2.エ
ピタキシャル層3.醸化膜層4.オーミック拡散領域1
1.シロットキー窓、チタン層5プデン層6を蒸着する
。ここでシ目ットキーとなるチタン層の上の金属(この
例ではモリブデン)の厚さはショットキーメタルよりも
約2倍程度厚くシ、かつエツチング速度の遅いものがよ
い。次に全面をフォトレジストアで覆った後、通常の写
真蝕刻法によりシロットキー窓上以外の7オトレジスト
を除去し、モリブデン層の一部を露出させる。次に残さ
れたフォトレジスト7金マスクとして塩素系ガス雰囲気
中で通常のドライエツチングを行なうことによりモリブ
デン層をエツチング除去し、チタン層5を露出させる(
第6図)。次にフォトレジストを除去した後、モリブデ
ンM6をエツチングマスクとして通常のイオンミリング
法によりチタン層5をエツチング除去する。このとき同
時にモリブデン層のエツチングされることが懸念される
が、モリブデン社チタンと比較してそのエッチレイトが
約171〜1.5程度であるξとと、モリブデン層の厚
さがチタン層の2倍と厚くなっていることから、かかる
問題は生じない。最後にオーミック拡散層表面の一部を
、露出させた後、アルミニウムを蒸着してショットキー
特性8とオーミック電極9とを形成する(第8図)。
A buried region 2. is formed in the semiconductor substrate 1 in the same manner as in the conventional manufacturing method. Epitaxial layer 3. Breeding film layer 4. Ohmic diffusion region 1
1. A Sirotchi window, a titanium layer 5 and a pudane layer 6 are deposited. The thickness of the metal (molybdenum in this example) on the titanium layer serving as the Schottky metal is preferably about twice as thick as the Schottky metal, and has a slow etching rate. Next, after covering the entire surface with photoresist, the seven photoresists other than those on the Sirotchi window are removed by ordinary photolithography to expose a part of the molybdenum layer. Next, the remaining photoresist 7 is used as a gold mask to perform normal dry etching in a chlorine gas atmosphere to remove the molybdenum layer and expose the titanium layer 5.
Figure 6). Next, after removing the photoresist, the titanium layer 5 is etched away by a normal ion milling method using molybdenum M6 as an etching mask. At this time, there is a concern that the molybdenum layer may be etched at the same time. Since it is twice as thick, this problem does not occur. Finally, after exposing a part of the surface of the ohmic diffusion layer, aluminum is deposited to form a Schottky characteristic 8 and an ohmic electrode 9 (FIG. 8).

以上の実施例かられかるように、本発明′fr適用した
チタンシプットキーダイオードにおいては、チタン層を
イオンミリング法によりエツチング除去するときのマス
クとして、フォトレジストではなくその上の金属層(モ
リブデン層)を用いているので、メタル再付着部分を大
巾に低減することができるようになり、その結果従来し
ばしば発生したアルミニウム等の配@電極の段切れ不良
をなくすることが可能となった。さらに又、イオンミリ
ング時の耐エツチングマスクとしてフォトレジストを用
いる必要がなくなったので、その結果従来しばしば発生
していた下層メダル(モリブデン層)の変色による特性
不良及び信頼度の低下をなくすることも可能となった。
As can be seen from the above embodiments, in the titanium shipput key diode to which the present invention is applied, the metal layer (molybdenum layer), it has become possible to greatly reduce the amount of metal re-deposition, and as a result, it has become possible to eliminate the disconnection defects of electrodes made of aluminum etc. that often occurred in the past. . Furthermore, since it is no longer necessary to use a photoresist as an etching-resistant mask during ion milling, it is possible to eliminate poor characteristics and lower reliability due to discoloration of the lower medal (molybdenum layer) that often occurred in the past. It has become possible.

。 尚本実施例においては、アルミニウム電極の侵入防止用
金属としてMoを用いたが、ドライエツチングの可能な
他の金属1例えばW、Ta等でも同様な効果が得られる
ことLいうまでもない。さらに本製法はシッットキーF
ET等他の半導体装置・にも同様に適用できる0
. In this embodiment, Mo was used as the metal for preventing intrusion of the aluminum electrode, but it goes without saying that similar effects can be obtained with other dry-etchable metals such as W and Ta. In addition, this manufacturing method uses Sittky F.
It can be similarly applied to other semiconductor devices such as ET.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は横形チタンク冒ットキーダイオードの平面図、
第2図〜第5図は従来製法を適用した場合の各工程にお
ける断面図、第6図〜第8図は本発明を適用した場合の
一実施例による各工程における断面図である。 1・・・・・・半導体基板、2・・・・・・埋込拡散層
、3・・・・・・エピタキシャル層、4・・・・・・酸
化膜層、5・・・・・・チタン層、6・・・・・・モリ
ブデン層、7・・・・・・フォトレジスト屑s8・・・
−・・り函ットキー電極、9・・団オーミッタ電極、1
0・・・・・・メタル再付着層、11・・・・・・オー
ミック拡散層。 代理人 弁理士  内 原   晋 ]A 」7゜ 第1図 め2聞 $3閃 磨4図 第5図 第6図 宅7図 第O図
Figure 1 is a plan view of a horizontal titanium cut key diode.
2 to 5 are cross-sectional views at each step when the conventional manufacturing method is applied, and FIGS. 6 to 8 are cross-sectional views at each step according to an embodiment when the present invention is applied. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Buried diffusion layer, 3... Epitaxial layer, 4... Oxide film layer, 5... Titanium layer, 6...Molybdenum layer, 7...Photoresist scraps s8...
-...Rebox key electrode, 9...Group ohmitter electrode, 1
0...Metal re-deposition layer, 11...Ohmic diffusion layer. Agent Patent Attorney Susumu Uchihara ] A 7゜ Figure 1, 2, $3, Senma, 4, Figure 5, Figure 6, House, Figure 7, Figure O

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上にショットキー市極とオーミック電極とを
形成する方法において、ショットキー電極構造としてシ
ョットキーメタル上に少なくとも異なるメタルR4t−
is以上設け、この異なるメタル層をマスクとしてその
下層のショットキーメタルをエツチングするようにした
ことを%徴とする半導体装置の製造方法。
In a method for forming a Schottky electrode and an ohmic electrode on a semiconductor substrate, at least a different metal R4t- is formed on the Schottky metal as a Schottky electrode structure.
A method for manufacturing a semiconductor device characterized by etching the underlying Schottky metal using the different metal layer as a mask.
JP10190583A 1983-06-08 1983-06-08 Manufacture of semiconductor device Pending JPS59227120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10190583A JPS59227120A (en) 1983-06-08 1983-06-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10190583A JPS59227120A (en) 1983-06-08 1983-06-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59227120A true JPS59227120A (en) 1984-12-20

Family

ID=14312919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10190583A Pending JPS59227120A (en) 1983-06-08 1983-06-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59227120A (en)

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