JPS5922600Y2 - linearizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a nonlinear double integral type linearizer that converts an analog input terminal into a linearized pulse width signal.

Conventionally, nonlinear double integral type linearizers have approximated the nonlinearity of the input voltage with a polygonal line having equally spaced polygonal points, and the number of polygonal points has determined the approximation accuracy of the linearizer.

Therefore, if an input terminal exhibits a different curve in only a part of the input range, it is necessary to increase the number of bending points in total in order to accurately approximate that part. It was not possible to make an approximation of

The present invention eliminates the drawbacks of the conventional device as described above and realizes a linearizer with a simple configuration that can perform high-precision approximation with a small number of bending points by making the intervals of bending points unequal. It is aimed at.

FIG. 1 is a block diagram showing an embodiment of the linearizer of the present invention.

In the figure, A1 is an operational amplifier, R1 and R2 are resistors, and C
1 is a capacitor, which constitutes an addition integrator INT.

SWl is a switch driven according to the reference signal Ps, S
W2 is a switch operated in response to the output signal 5out.

COM is a comparator that compares the output Eo of the summing integrator INT with a zero level, and NOR is an output signal S to which the output Sc of the comparator COM and the reference signal Ps are applied.

This is a logic circuit that generates ut, and here a NOR gate is shown.

INV is an inverting circuit.

CPG is a pulse generator that generates clock pulses Pc according to an arbitrarily set program, COU is a counter that counts clock pulses Pc, and ROM stores arbitrary digital values, and the stored contents are changed according to the count value of counter COU. The digital memory DA that follows is a digital-to-analog converter (hereinafter abbreviated as a D/A converter) that converts the output of the digital memory ROM into an analog voltage E1.

The input voltage E+n is input to the summing integrator I via the switch SW1.
The output E1 of the D/A converter DA is applied to the summing integrator INT via the switch SW2.

The operation of the linearizer of the present invention configured as described above will be explained as follows using the waveform diagram shown in FIG.

If the reference signal Ps is a pulse width signal having a waveform as shown in the figure, the switch SW1 is turned on during the period in which the reference signal Ps is at the "H" level, and the summing integrator INT integrates the input voltage E1o.

At this time, the output Eo of the summing integrator INT becomes a negative value, so the output Sc of the comparator COM goes to "L" level and becomes the output signal S of the logic circuit NOR.

Ul is also at "L" level.

In response to this, switch SW2 is turned off.

Also, the output signal S. Since ul is applied as a reset signal to the counter COU via the inversion circuit INV,
The count value of the counter COU is zero.

Next, a certain period of time has passed since the rise of the reference signal Ps,
When the reference signal Ps reaches the “L99 level,” the logic circuit NO.
R's output signal S.

Since uo is at the ゛°H゛ level, switch SW
Switch SW2 is turned on instead of switch SW1.

Output signal S. Since Ul releases the reset of the counter COU and also provides a 1~trigger to the pulse generator CPG, the clock pulse Pc is applied to the counter COU.

The digital memory ROM outputs the stored contents of the address specified by the count value of the counter COU, and the digital signal is converted to an analog voltage El by the D/A converter DA.
is converted into summing integrator INT via switch SW2.
is applied to

Here, the summing integrator INT integrates the analog voltage El in the opposite direction, and when the integral output Eo becomes zero, the output Sc of the comparator COM is inverted and becomes the output signal S of the logic circuit NOR.

Since ut becomes the "L" level, the switch SW2 is turned off and the integrating operation of the summing integrator INT is stopped.

Also, the output signal S. ut is applied to the counter COU via the inverting circuit INV to reset the counter COU.

In this way, the input voltage Eln causes the output signal S to have a pulse width corresponding to its magnitude.

However, since the magnitude of the analog voltage El that integrates the summing integrator INT in the reverse direction changes with the application of the clock pulse Pc, the output signal S.

ut has non-linearity with respect to the input voltage Ein.

Therefore, by appropriately selecting the degree of change in the analog voltage E1, the output signal S is linearized from the input voltage EIn.

We can obtain U. As shown in FIG. 2, the integral waveform of the analog voltage E1 is a polygonal line, and by approximating the nonlinearity of the input voltage E1o with this polygonal line, the input voltage E1n can be linearized.

Here, the slope of the broken line corresponds to the content stored in the digital memory ROM, and the intervals t1 to t3 between the broken points correspond to the period of the clock pulse Pc.

Therefore, in a complicated part of the bend, the clock pulse Pc
By shortening the cycle of Pc, the interval between the bending points can be narrowed, and in the case of a simple bend, the period of the clock pulse Pc can be lengthened to widen the interval between the bending points, and high-precision approximation can be performed with a small number of bending points. be able to.

Note that the period of the clock pulse Pc is preprogrammed in the pulse generator CPG according to the nonlinearity of the input voltage EIo, and the pulse generator CPG generates the clock pulse Pc by changing the period with time. and applies it to the counter COU.

FIG. 3 shows the configuration of another embodiment of the linearizer of the present invention.

The device shown in the figure is the nonearizer shown in FIG.
and a select signal generator SSG.

In the figure, the same parts as in FIG. 1 are designated by the same reference numerals.

Oscillator O3C generates four pulse signals P1 to P with different periods.
4, and its cycles T1 to T4 are selected as follows, for example.

Data selector DS outputs signals a,
Predetermined pulse signals P1 to P4 are selected according to the state of (l) and supplied to the counter COU as a clock pulse Pc.

The select signal generator SSG generates a binary select signal a,
The relationship between the signal level and the pulse signals P1 to P4 selected by the data selector DS is as shown in the following table.

FIG. 4 is a waveform diagram showing the relationship between the select signals a, l) and the clock pulse Pc output from the data selector DS.

As shown in the figure, the period of the clock pulse Pc can be changed arbitrarily by controlling the state of the select signal a, 1).

Here, the select signal generator SSG is programmed to change the combination of the select signals a, l) over time to set the clock pulse Pc, that is, the interval between the breakpoints, to a desired state.

In the example shown in FIG. 4, the clock pulse Pc is generated so that the interval between the bending points becomes gradually narrower.

The operation of other parts is the same as that of the apparatus shown in FIG. 1 described above.

As explained above, the linearizer of the present invention integrates the input voltage for a certain period of time, then integrates the reference voltage whose magnitude changes over time in the opposite direction, and generates a pulse corresponding to the time until the integrated output becomes zero. In a nonlinear double-integration type linearizer designed to obtain an output signal having a width, the output of a digital memory read out according to the count value of a counter that counts clock pulses is D/A converted to generate a reference voltage. Since the period of this clock pulse is changed according to a preset program, the intervals between the breakpoints are set at irregular intervals, and a linearizer that can perform high-precision approximation with a small number of breakpoints can be created with a simple configuration. It can be realized.

[Brief explanation of the drawing]

1 and 3 are configuration diagrams showing an embodiment of the linearizer of the present invention, and FIGS. 2 and 4 are waveform diagrams for explaining its operation. A1... operational amplifier, R1, R2...
Resistor, C1... Condenser, INT...
...Summing integrator, SWl, SW2...Switch, COM...Comparator, NOR...Logic circuit, INV...Inverting circuit, CPG... ...
・Pulse generator, COU...Counter, ROM
...Digital memory, DA...Digital-to-analog converter, O20...Oscillator, DS...Data selector, SSG...
・Select signal generator.

Claims (1)

[Scope of utility model registration request] A pulse generator that generates clock pulses and changes the period of the clock pulses according to a preset program; a counter that counts the clock pulses; It is equipped with a digital memory that outputs data in accordance with numerical values, and a digital-to-analog converter that converts the output of this digital memory into an analog reference voltage, and after integrating the input voltage for a certain period of time, converts the reference voltage in the opposite direction. A linearizer that obtains an output signal having a pulse width corresponding to the time it takes for the integrated output to become zero.