JPS5829219A - Analog-to-digital converter - Google Patents

Abstract

PURPOSE:To obtain a high-precision efficient converter by increasing an amplifier gain, preset in an analog-to-digital converter (ADC), until the MSB of the ADC reaches ''1''. CONSTITUTION:An analog input is held by a sample holding circuit 34 with the output of a controller 32. The output of the holding circuit 34 is applied to an ADC13 through a programmable gain amplifier 11 and a sample holding circuit 12. At this time, the gain of the amplifier 11 is increased through the controller 32 by the power of ''2'' until the MSB of the ADC13 reaches ''1''. when the MSB reaches ''1'', the output of the amplifier 11 at that time is held by the holding circuit 12 and applied to the ADC13. A digital value obtained by controlling the amplifier 11 is added to the output digital signal of the ADC13 and the resulting signal is outputted to a data bus 1e.

Description

[Detailed description of the invention] Kimizuka converts analog quantities into digital quantities, improvement 1
In order to install the analog-to-digital converter Kll.

Conventionally, when converting an analog quantity to a digital quantity,
It has long been customary to determine the gain constant of an analog-to-digital converter so that the maximum value of the analog quantity becomes the maximum value of the digital quantity.

In this case, the analog quantity (hereinafter referred to as resolution) to which the digital quantity corresponds to IK is determined by a one-way converter. For this reason, in systems that selectively switch multiple analog inputs and convert analog to digital,
The maximum value of each input point varies widely, so fixing the input gain of the converter will reduce the resolution for small input points, resulting in poor accuracy. Further, it is expensive and difficult to adjust the gain by having a gain amplifier for each input point.

Conventionally, attempts have been made to solve the above problems with a circuit configuration as shown in FIG. That is, the analog input 1a shown at 1 in FIG.
When a computer (not shown) writes a gain constant into the register xsK, the analog switch inside the programmable gain amplifier 11 is driven by the deder 174C, and the analog input 1m is multiplied by the specified gain constant. is output.

The sample and hold circuit 12 holds the analog input signal 1G so that it does not change during analog-to-digital conversion. , and generates a conversion start signal 1hi to the analog-to-digital converter 13. Using this signal, the analog signal IC, which is constant during conversion, is converted into a digital quantity by the analog-to-digital converter 13, and a conversion completion signal If is generated. Then, read the digital quantity from the computer via the buffer 14 and divide this data by the specified gain constant).
The actual hexagonal value can be determined by specifying the gain constant for each input point using a computer, amplifying it with a programmable gain amplifier, and converting it from analog to digital. It is possible to configure a system with a wide dynamic range. However, the determination of the gain constant is processed by a computer, and the conversion with the maximum dynamic range is not necessarily 1 kvh. Determine the gain constant so that analog to digital conversion can be performed at the maximum range,
Read this gain constant and converted digital quantity using a computer.9
, it is an object of the present invention to provide an analog-to-digital converter that is more accurate and efficient through processing and that does not have the above-mentioned drawbacks.

Hereinafter, the present invention will be described with reference to an embodiment shown in the drawings. FIG. 2 is a block diagram of the Progera i pull gain amplifier. In the figure, numeral 23 is an operational amplifier forming an inverting amplifier circuit. In this circuit, feedback resistors R, 2B, 4t
By turning on the L-nR with the analog switch group 22, the amplification factor is changed to 1x, 2x, 4x, etc. by the output signal of nfl and the decoder 17.

FIG. 3 shows a principle diagram of a sequential comparison type analog-to-digital converter. In the figure, the control circuit 29 is activated by the conversion start signal in synchronization with the clock signal.
By fON, digital-to-analog converter 2
3 outputs a voltage of V/2 of the reference voltage V. The comparator 28 then compares the input voltage with the output of the digital-to-analog converter 26. If the input voltage exceeds the first manual comparison value V2, the # control circuit 29 turns on the next bit fON at the next clock. This means that the input voltage t-3V/
Comparing with the voltage of 4, it becomes K. If the input voltage (2) is smaller than the first input comparison value (2), the control circuit 29 resets the first bit and turns on the next bit at the next clock. This means that ■ the input voltage is compared with the negative voltage.

In this way, the lower bits are sequentially turned on every clock, digital-to-analog converted, compared with the input voltage, and the previous bits are reset according to the result, and the comparison is continued until the last least significant bit is determined. The serial output is serially output to the outside in synchronization with the set/reset state clock signal, and the parallel output is output in parallel when the least significant bit is determined. The status is an output signal indicating that conversion is in progress. ◎Figure 4 is a block diagram showing the configuration of the present invention.

In the figure, the programmable gain amplifier 11 is the same as that explained in FIG. 42 above. The sample and hold circuits 12 and 34 hold the analog signal ICt constant during analog-to-digital conversion. The analog/digital converter 44513 is the sequential comparison type analog/digital converter described in FIG. Buffer 14
is for outputting data ld to data bus leK when a digital amount t-m is received from the computer. controller 3
2 is a control circuit for realizing the present invention. 31 is
This is a shift register that receives shift pulses from the controller 32 for shifting. The buffer 33 outputs the output of the shift register 31 to the data bus 1e when the data of the shift register 31 and the marigain constant are read by a computer.

Next (the operation of FIG. 444 will be explained with reference to FIG. 5. In other words, in FIG. 5, from the computer to the data bus t
When the e6c conversion start signal COV・8T (Ig) is output, the controller 32 outputs a signal 8/)(-A (3g) for switching from sample to hold to the sample/hold circuit 34, and Human power 1a
Hold tP. Further, the controller 32 outputs a signal 8/HB (3a) for switching from sample to hold to the sample/hold circuit 12, and holds the output 1bl of the programmable gain amplifier 11.

In addition, the analog/digital conversion start pulse/D
・When 8 T 0It- occurs, as explained in Figure 3 of Mayuki, the built-in clock signal compares the most significant pit in order, and the result is sent to the clock signal CLOCK.
Serial output 8・D・0UT (3
d) and is input to the controller 32.

AND 8DO to controller 32 FiCLOC'
When the shift pulse 8PPL8 (3s) is generated in the UT, the shift register 31 becomes 8・RIG 1, 2,
Shift the Kl data as shown in 4..., hold it in the sample/hold circuit 34 by 1, 2, and 4 times with respect to the programmable gain amplifier 11, and amplify it by analog human power 1a f. Obtains 1bi amplifier output. ? !
In diagram A5, analog human power is 2V K, 4v, Bv
This shows how it is amplified.

Here, if the 7 real output 8・DOUi' (3d) of the analog-to-digital converter 1j reaches IK, increasing the gain any further will cause the input range to be exceeded.
The programmable gain amplifier 11 is fixed here. This is the range check cycle for analog input. Next, when 8・DOUT (3d) becomes 1, the controller 3
2 is a sample [No. 8/II (3a) t-output, samples the analog signal 1b multiplied by 4 with the programmable gain amplifier 7'll, holds it after a sufficient sampling time, and outputs the analog signal 8 /H-0UT (I
C) is held constant.

At this time, the sample/hold circuit 34 at the previous stage is released from hold and placed in a sample state.

Next, for this analog input signal, a conversion start signal A7'o-s'r (3b
) Output from the t-controller 32 and compared with the internal clock signal until the most significant bit to the least significant bit is determined, and when analog-to-digital conversion is completed,
Since the completion signal 8TATU8 (3f) is output from the analog/digital converter 13, the computer uses this signal to read the digital quantity 1di via the buffer 14, and also transfers the contents of the gain constant shift register 31 to the buffer 33. By reading through the , the actual input value can be read.

In the example of Figure 5, if the actual input voltage is 2V,
It is multiplied by 4 in the input range check cycle, amplified to 8V by the programmable gain amplifier 11K, and converted into a digital quantity by the analog-to-digital converter 13 (the input digital signal is unipolar with the resolution of the analog-to-digital converter 18 bits). fi k quantity u 256
XA! g-=204.8=11001100
to Nine, the gain constant can be read as 4 times, so the actual human power is 11001100-)-4-t' 0
OI100IB: Yes. In other words, the analog quantity is 2V.
K-phase teeth.

In this way, according to the present invention, an effective analog-digital device can be provided that is capable of converting a small scale with high precision.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional analog-to-digital converter, Figure 2 is a block diagram of a programmable gain amplifier,
Fig. 3 is a basic diagram of a basic flashback comparison type analog-to-digital converter, Fig. 4 is a block diagram of an analog-to-digital converter showing an embodiment of the present invention, and Fig. 5 is an operation of the present invention. 2 is a time chart of the main components.

Claims (1)

[Claims] An analog-to-digital converter equipped with a programmable gain amplifier in the first stage automatically determines the gain constant of the programmable gain amplifier according to the analog input level and performs analog-to-digital conversion at the maximum range. The controller is an analog-to-digital converter whose purpose is to convert analog input signals with high accuracy.