JPS59225535A - Composite component for loading semiconductor - Google Patents

Composite component for loading semiconductor

Info

Publication number
JPS59225535A
JPS59225535A JP10141483A JP10141483A JPS59225535A JP S59225535 A JPS59225535 A JP S59225535A JP 10141483 A JP10141483 A JP 10141483A JP 10141483 A JP10141483 A JP 10141483A JP S59225535 A JPS59225535 A JP S59225535A
Authority
JP
Japan
Prior art keywords
alloy
frame
composite
ceramic
ceramic plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10141483A
Other languages
Japanese (ja)
Other versions
JPH0376579B2 (en
Inventor
Mitsuo Osada
光生 長田
Sogo Hase
長谷　宗吾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP10141483A priority Critical patent/JPS59225535A/en
Publication of JPS59225535A publication Critical patent/JPS59225535A/en
Publication of JPH0376579B2 publication Critical patent/JPH0376579B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain the title component at a low cost and high performance by a method wherein a ceramic plate or frame is brought to junction at the same time that Cu-W alloy is obtained in the process of impregnating Cu, when the alloy of cu-W, etc. is obtained by impregnation of Cu to a porous body of W, etc. CONSTITUTION:The ceramic plate or frame 12 having a metallized layer 13 and the porous body 11 of W, Mo, or W-Mo alloy are laminated, and Cu is impregnated thereto (process S) at a temperature over the melting point of Cu in a non-oxidizing atmosphere; thereby bringing both to junction with the Cu layer 14. As a result, the composite component having a thermal conductivity of the junction layer more excellent than that of the coventional component brazed with Ag solder and a low manufacturing cost. When the ratio of Cu in the component is 5-20wt% at this time, the rate of thermal epansion is kept in a range of 6-8(X10<-6>/ deg.C), which is approximate to the rate of expansion of ceramic at 6.5-7.5(X10<-6>/ deg.C), and accordingly the junction between the ceramic plate or frame and the Cu-W, Cu-Mo, and Cu-W-Mo becomes dense.

Description

【発明の詳細な説明】 この発明は製造コストが安価で熱伝層率のプぐれた０Ｌ
−Ｗ、侃−出、α−Ｗ−ｒ％などの複合合金とセラミッ
ク板または枠との複合部品に関りるものである。DETAILED DESCRIPTION OF THE INVENTION This invention is an 0L with low manufacturing cost and excellent thermal conductivity.
The present invention relates to a composite part made of a composite alloy such as -W, Kanade, α-W-r%, etc., and a ceramic plate or frame.

近年ＩＣの演詐速度の向上、トランジスタの電気容量の
増大、Ｇａ　−Ａｓ、　Ｆ　Ｅ　１−の出現等により、
半導体素子の駆動向に半導体素子に発生ずる熱をいかに
放熱させるがという点が大きな問題となっている。In recent years, due to improvements in the performance speed of ICs, increases in the capacitance of transistors, and the appearance of Ga-As and FE1-,
A major problem is how to dissipate the heat generated in the semiconductor element in the driving direction of the semiconductor element.

半導体素子内に発生づる熱は半導体素子が搭載され、半
導体素子裏面と接合された基板を通してパッケージ外へ
排出される。Heat generated within the semiconductor element is discharged to the outside of the package through the substrate on which the semiconductor element is mounted and bonded to the back surface of the semiconductor element.

従ってこの基板材料には熱伝導度が高い材料を用いるこ
とが好ましい。Therefore, it is preferable to use a material with high thermal conductivity for this substrate material.

ところで近年前記パッケージとしてセラミツ、りを用い
たセラミックパッケージが・多用されている。By the way, in recent years, ceramic packages using ceramics and glue have been frequently used as the packages.

このパッケージの場合、前記基板が電極取出し用のセラ
ミック板または枠と一体化されている。従って基板材料
として／Ｖ　２０３を主成分とする磁器を使用する場合
には、電極取出し用のセラミック様または枠と一体焼成
されるため問題ないが、熱伝導性を向上させるためＷや
出など電極取出し用のセラミック板または枠と異種の材
料を基板材料として用いる場合、以下の如き問題が生ず
る。In the case of this package, the substrate is integrated with a ceramic plate or frame for taking out the electrodes. Therefore, when using porcelain whose main component is /V 203 as the substrate material, there is no problem because it is fired integrally with the ceramic or frame for taking out the electrodes, but in order to improve thermal conductivity, When a material different from the ceramic plate or frame for taking out is used as the substrate material, the following problems occur.

即ちＷや出等を基板材料として用いた場合、電極取出し
用のセラミック板（または枠）との接合は通常銀ロウに
よるロウ付は方法が用いられる。That is, when W or copper is used as the substrate material, soldering with silver solder is usually used to bond it to a ceramic plate (or frame) for taking out the electrodes.

この場合、Ｗや１などはセラミックとの熱膨張率の差が
大きいため、ロウ付は工程における加熱後の冷却時に熱
歪によりセラミック板または枠が破損Ｊるとう問題が生
ずる。In this case, since W, 1, etc. have a large difference in coefficient of thermal expansion from ceramic, there is a problem in brazing that the ceramic plate or frame may be damaged due to thermal strain during cooling after heating in the brazing process.

このため、熱膨張率がセラミックと近いＦｅ　　ＮＬ金
合金たはＦｅ−ＮｉＣｏ合金の薄板を基板とセラミック
板または枠の間に介在させることが行なわれているが、
かかる方法は熱伝導上好ましくない。For this reason, a thin plate of FeNL gold alloy or Fe-NiCo alloy, which has a coefficient of thermal expansion close to that of ceramic, is interposed between the substrate and the ceramic plate or frame.
Such a method is unfavorable in terms of heat conduction.

一方、熱伝導性が良く、熱膨張率もセラミックまたは枠
に近いＢｅＯを用いることが考えられるが、Ｂｏｏは毒
性を右するため、取扱いや製造が困難であり、さらに入
手にも問題がある。On the other hand, it is conceivable to use BeO, which has good thermal conductivity and a coefficient of thermal expansion close to that of ceramic or frame, but since Boo is toxic, it is difficult to handle and manufacture, and there are also problems in obtaining it.

本発明者らは、゛りでにかかる目的に適りる熱伝導度が
高く、かつセラミックと熱膨張率の近似した材料として
Ｗ、１１１ｏまたはＷ−Ｎｏの合金粉末の多孔体に髄を
含浸して得る偽−Ｗ、Ｃｔｔ−出、伍−Ｗ−Ｎｏ複合合
金を見出し、さきに特許出願した（特願昭５８−１０７
９０号、特願昭５８−１０７９１号）。The present inventors impregnated pith into a porous body of alloy powder of W, 111o, or W-No as a material that already has high thermal conductivity and has a coefficient of thermal expansion similar to that of ceramic. I discovered the fake-W, Ctt-ex, and 5-W-No composite alloys that could be obtained by doing this, and filed a patent application (Japanese Patent Application No. 107-1981).
No. 90, Japanese Patent Application No. 58-10791).

なお、これら伍−Ｗ１負−出、偽−Ｗ−重合金の製造法
としてはＷ、−またはｗ−ｈ合金粉末を成形（プレスま
たは押出し）し、これを所定の空孔率を有する多孔体に
焼成したのち、侃を含−浸することにより、特性のより
優れた材料を得ることができることを見出し、さきに特
許出願した（特願昭５８−１７１４０号、５８−１７１
４１号）。The method for producing these 5-W1 negative and pseudo-W-heavy alloys involves molding (pressing or extruding) W, - or wh alloy powder, and forming it into a porous body having a predetermined porosity. It was discovered that a material with better properties could be obtained by impregnating the material after firing, and filed a patent application (Japanese Patent Application No. 58-17140, 58-171).
No. 41).

この発明は、Ｗ等の多孔体に廓を含浸して伍−Ｗ等の合
金を得る際に、この伍の含浸■稈においてセラミック板
または枠をＣｕ−Ｗ合金を得ると同時に接合りることに
より安価かつ高性能の複合部品が１！１られることに着
眼したものである。The present invention is to impregnate a porous body such as W with copper to obtain an alloy such as 5-W, and to join a ceramic plate or frame at the culm of this 5-impregnated material at the same time as obtaining the Cu-W alloy. The focus is on the ability to produce composite parts that are both inexpensive and high-performance.

通常へ−Ｗ１伍−出あるいはＣｕ−Ｗ−１’に＋合金を
放熱板として用いた半導体パッケージは第１図（ａ　）
および（ｂ）に示すような４ｉ造である。Figure 1 (a) shows a semiconductor package in which + alloy is used as a heat dissipation plate for normal -W15- or Cu-W-1'.
and 4i construction as shown in (b).

（Ｃｕ−Ｗ合金の場合を例として示す。）即ち、１は（
ｘ−Ｗ合板よりなる基板、２はパッケージ材であるセラ
ミック枠である。そしてこのセラミック枠２はＣｕ−Ｗ
合金基板１と接合される部分にメタライズ層３が設番プ
られ、このメタライズ層３とＱｔ−Ｗ合金基板１が銀ロ
ウなどによってロウ付けされている。なお４は半導体素
子、５はリードフレーム、６はボンディングワイヤーで
ある。(The case of Cu-W alloy is shown as an example.) That is, 1 is (
The substrate is made of x-W plywood, and 2 is a ceramic frame that is a packaging material. And this ceramic frame 2 is Cu-W
A metallized layer 3 is provided at a portion to be bonded to the alloy substrate 1, and the metallized layer 3 and the Qt-W alloy substrate 1 are soldered with silver solder or the like. Note that 4 is a semiconductor element, 5 is a lead frame, and 6 is a bonding wire.

このような半導体パッケージを組立でる場合についての
べると、第２図に示すように、通常Ｑ−Ｗ合金などの基
板１とセラミック枠または板２との接合は、セラミック
枠または板２にＷ１翫などを焼イ１けて形成したメタラ
イズ層３とｃ＋４−Ｗ合金等の基板１またはその上面の
Ｎ、あるいは負のめっき面（図示せず）とを基板１上に
銀ロウ７をおいて積み重ねて加熱し、ロウイ４けにて行
なわれている。When assembling such a semiconductor package, as shown in Fig. 2, the bonding between the substrate 1 such as Q-W alloy and the ceramic frame or plate 2 is usually carried out by attaching a W1 rod or the like to the ceramic frame or plate 2. The metallized layer 3 formed by baking the metallized layer 3 and the substrate 1 made of c+4-W alloy or the like or its upper N or negative plating surface (not shown) are stacked with silver solder 7 placed on the substrate 1. It is heated and carried out in a rowi bowl.

この場合銀ロウ７としＣはＡｇとへの共晶合金ロウが用
いられることが多く、これは６価であるとともに熱伝導
がよくないという欠点を有している。In this case, silver solder 7 and C are often used as a eutectic alloy solder with Ag, which has the disadvantage of being hexavalent and having poor thermal conductivity.

この発明は上記のような銀ロウによる基板とヒラミック
枠または板の接合の欠点を解消し、製造コストが安価で
かつ熱伝導のすぐれたＣＬＬ−Ｗ等複合合金放熱板とヒ
ラミック枠または板よりなる複合部品を提供しようとす
るものである。This invention eliminates the drawbacks of bonding the substrate and the helical frame or plate using silver solder as described above, and is made of a composite alloy heat dissipation plate such as CLL-W, which is inexpensive to manufacture and has excellent heat conduction, and the helical frame or plate. The aim is to provide composite parts.

以下この発明を第３図にもとづいて説明する。This invention will be explained below based on FIG.

即ちこの発明は、予めメタライズしてメタライ　　　。That is, in this invention, metallization is performed by pre-metallizing.

ズ層１３を有するセラミック板または枠１２とＷ、Ｎ。Ceramic plate or frame 12 with a layer 13 and W,N.

あるいはＷ−ＭＯ合金の多孔体１１を用意し、このセラ
ミック板または枠１１のメタライズ層１３と前記多孔体
１１を積層し、これに非酸化性雰囲気中で負の融点をこ
える温度にて気を含浸す′ること（■程Ｓ）により、侃
層１４にて両者を接合するものであり従来の銀ロウによ
りロウ付けされた複合部品に在べて接合層の熱伝導度が
すぐれ、かつ製造コストが安価な複合部品が得られるの
である。Alternatively, a porous body 11 of W-MO alloy is prepared, the metallized layer 13 of this ceramic plate or frame 11 and the porous body 11 are laminated, and this is heated in a non-oxidizing atmosphere at a temperature exceeding the negative melting point. By impregnating (Step S), the two are bonded at the side layer 14, and the bonding layer has excellent thermal conductivity and is easy to manufacture compared to composite parts soldered with conventional silver solder. A composite part with low cost can be obtained.

なおこの発明において使用するセラミック板または枠の
材料としテハ、＃、０３．５ＬｓＮ４　、ＳＬＣあるい
はこれらの複合セラミックなど半導体パッケージに使用
されるものであればよく、特に限定されない。The material of the ceramic plate or frame used in the present invention is not particularly limited as long as it is used in semiconductor packages, such as Teja, #, 03.5LsN4, SLC, or composite ceramics thereof.

またＷ１出あるいはＷ−田合金などの多孔体としては、
本発明者らが既に特許出願した特願昭５８−１５１２１
、特願昭５８−１５１２２に記載の如く、平均粒径１〜
４０μのＷ粉末、臨粉末あるいはＷ−出合金粉末に鉄族
元素を０．０２〜２重量％添加した粉末を加圧成形後、
非酸化性雰囲気で焼結した焼結多孔体であって、これに
αを５〜２０重司％のム含浸比率となるに適した空孔率
を有するものがのぞましい。In addition, as a porous body such as W1 or W-D alloy,
Patent application No. 58-15121, which the present inventors have already applied for
, as described in Japanese Patent Application No. 58-15122, the average particle size is 1 to 1.
After pressure molding a powder in which 0.02 to 2% by weight of iron group elements is added to 40μ W powder, raw powder, or W-depleted alloy powder,
A sintered porous body sintered in a non-oxidizing atmosphere and having a porosity suitable for obtaining a mu impregnation ratio of 5 to 20% α is desirable.

この発明に’ＵＣｕ−Ｗ、Ｃｕ−１’ｂ、Ｑｉ−Ｗ−重
合金からなる半導体搭載用複合部品中の仮止を５〜２０
重量％とするのは、熱Ｗ、服率を６〜ａ（ｘ１０／℃）
の範囲に保たせるためであり、これはセラミックの熱膨
張率６．５〜７．５　（ｘ　１０／’Ｃ）に近似させる
ことによってセラミック板または枠とＱｔ−Ｗ、　Ｃｔ
ｔ−ＭＯｌｃｕ−ｗ−ｈとの接合を密にするためである
。This invention provides temporary fixing of 5 to 20% in semiconductor mounting composite parts made of 'UCu-W, Cu-1'b, and Qi-W-heavy alloys.
Weight % is based on heat W and clothing rate of 6 to a (x10/℃)
This is done in order to keep the coefficient of thermal expansion of ceramic within the range of 6.5 to 7.5 (x 10/'C) to maintain the relationship between the ceramic plate or frame and Qt-W, Ct.
This is to make the bond with t-Molcu-wh dense.

またこの発明において、複合部品中に鉄族元素を０．０
２〜２重量％含有させるのは、Ｗｌ−１Ｗ−ＭＯ粉末を
焼成して焼結多孔体を得るに際し、これらＷ、出、Ｗ−
出粉末は融点が高いために単独でその圧粉体を焼結する
場合、所定の密度、空孔率の焼結体を得ようとすると高
温焼結が必要である。In addition, in this invention, 0.0% of the iron group element is contained in the composite part.
The content of Wl-1W-MO powder at 2 to 2% by weight is used when obtaining a sintered porous body by firing Wl-1W-MO powder.
Since the raw powder has a high melting point, if a green compact is sintered alone, high-temperature sintering is required in order to obtain a sintered body with a predetermined density and porosity.

ところが鉄族元素（Ｆａ、Ｃｏ、ＮＬ）はタングステン
と比較的低温で固溶体を作るため、Ｗ粉末、出粉末、Ｗ
−ル粉末に微量の鉄族元素を添加して焼結することによ
り、無添加の場合に比べて大幅に低い温度で同一空孔率
を持つ焼結多孔体が得られるためである。However, iron group elements (Fa, Co, NL) form solid solutions with tungsten at relatively low temperatures, so
This is because by adding a small amount of iron group element to the metal powder and sintering it, a sintered porous body having the same porosity can be obtained at a significantly lower temperature than when no addition is made.

そしてこのような効果のある鉄族元素の争を０．０２〜
２重量％とするのは、０．０２重Ｍ％以下では添加効果
なく、また２重量％をこえるど負の含浸時にＱ中への鉄
族元素の固溶により熱伝導度が低下するためである。And the content of iron group elements that have such an effect is 0.02 ~
The reason why it is set at 2% by weight is that if it is less than 0.02% by weight, there is no addition effect, and if it exceeds 2% by weight, the thermal conductivity will decrease due to solid solution of iron group elements in Q during negative impregnation. be.

次にこの発明の複合部品を得るに当っての生産コスト面
からの利点についてのべると次の通りである。Next, the advantages in terms of production cost in obtaining the composite parts of this invention are as follows.

即ち、従来のＱｔ−Ｗ等複合合金放熱板とメタライズ層
を有づるセラミック板を銀ロウ付けする場合には、この
銀ロウ付けを容易にするために、伍−Ｗ等へのＮＬ、Ｃ
ｕの表面処理工程あるいは銀Ｏつ付は工程における加熱
処理が必要であるが、この発明においてはＷ、ＭＯｌｗ
−ｘ多孔体とメタライズ層を有するセラミックス板また
は枠とをｖ４重ねて偽を含浸させるだけであるから、従
来法におりる銀ロウイ１け接合に比べると、高価な銀ロ
ウ材を必要としないこと、従って銀ロウ付けを容易にす
るための（ＳＬ−Ｗ等への表面処理工程が不要であるこ
と、など生産上の工程数をかなり減することができ、生
産コストの面で大きな利点を有するのであり。That is, when silver-brazing a conventional composite alloy heat sink such as Qt-W and a ceramic plate having a metallized layer, in order to facilitate this silver brazing, NL, C to Go-W, etc.
The surface treatment process of u or silver O attachment requires heat treatment in the process, but in this invention, W, MOLw
- Since the porous body and the ceramic plate or frame with the metallized layer are simply overlaid and impregnated with the material, expensive silver brazing material is not required compared to the conventional method of joining with one piece of silver brazing material. Therefore, it is possible to considerably reduce the number of production steps, such as eliminating the need for a surface treatment process for SL-W, etc., to facilitate silver brazing, and has a great advantage in terms of production costs. I have it.

またこの発明の複合部品の性能面での特徴は、銀ロウ付
は層がないから複合部品の上にＳ＝などの半導体素子を
搭載する場合、銀ロウを使用した場合に比べて熱伝導性
のよいへが接合層に存在するために、半導体素子中で発
生する熱をパッケージ系外へ排出する場合に良好な特性
を承りのぐある。In addition, the performance characteristics of the composite parts of this invention are that since there is no layer in silver soldering, when a semiconductor element such as S = is mounted on the composite parts, it has a higher thermal conductivity than when silver soldering is used. Since the bonding layer has a strong bonding layer, it has good characteristics when discharging the heat generated in the semiconductor element to the outside of the package system.

以下この発明を実施例により説明する。This invention will be explained below with reference to Examples.

実施例 ２〜３μのＷ粉末に粘結材として１申ｍ％のカンファー
を加え、これを３０ｘ　３０Ｘ　、１ｍｍの大ぎさに３
ｔ／４の圧力を加えて型押しした。次いでこの型押体を
Ｈ２ガス雰囲気中８００℃で加熱してカンファーを分解
蒸発させたのち、１）、ガス雰囲気中で１５００℃にて
焼成し、Ｗの多孔体を得た。Example 2 - 1 m% of camphor was added as a binding agent to W powder of 3 μm, and this was mixed into 30×30×, 1 mm size.
Embossing was performed by applying a pressure of t/4. Next, this embossed body was heated at 800° C. in an H2 gas atmosphere to decompose and evaporate camphor, and then 1) fired at 1500° C. in a gas atmosphere to obtain a porous W body.

このＷ多孔体にＷにて一面をメタライズした＃　２０゜
板のメタライズ面を合わせて積重ねたのち、Ｈ２ガス雰
囲気中でこの積重ね状態のＷ多孔体中に係を含浸させ、
メタライズ面にて侮によって接合された／Ｖ　２０３と
ＣｕｌＯ％−Ｗ９０％（７）ＣＬＬ−Ｗ合金の複合体を
　得　ｌこ　。#20° plates, one side of which was metallized with W, were stacked on this W porous body with their metallized surfaces aligned, and then the stacked W porous body was impregnated with a material in an H2 gas atmosphere.
A composite of /V203 and CulO%-W90% (7) CLL-W alloy was obtained by bonding on the metallized surface.

かくして得られた複合体と予め調整した同一組成のＣｔ
ｔ−Ｗ合金およびＷでメタライズしたＭ　２０３板をＷ
のメタライズ面を介してＡｇ−Ｃｕ共共合合金ロウてロ
ウ付けした複合体について、接合面を通し熱伝導性を測
定したところこの発明により１９られた複合体は５０％
良好な熱伝導性を示した。The thus obtained composite and Ct of the same composition prepared in advance
M 203 plate metalized with t-W alloy and W
When thermal conductivity was measured through the bonded surface of a composite made by brazing Ag-Cu co-conjugated alloy through the metallized surface of
It showed good thermal conductivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ　）および（ｂ）は半導体パッケージの構造
を示す断面図、第２図は従来の銀ロウイリは方法による
複合体製造工程の説明図、第３図はこ　　　゛の発明の
複合部品を得る工程説明図である。 代　　埋　　人　　弁理士　　和　　１）　　１１１１
第１ 第２図 図 第３図Figures 1 (a) and (b) are cross-sectional views showing the structure of a semiconductor package, Figure 2 is an explanatory diagram of the composite manufacturing process using the conventional silver-lowering method, and Figure 3 is the composite component of this invention. FIG. Substitute Patent Attorney Kazu 1) 1111
1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】 （１１Ｃｔｔ−Ｗ、侮−比、あるいは伍−Ｗ−１などの
合金を放熱用基板として用いる半導体搭載用複合部品に
おいて、Ｗ、Ｎｏなどの金属にて予めメタライズしたセ
ラミック板または枠のメタライズ面とＷ、ＭＯまたはＷ
−１％合金粉末を焼成して得た多孔体を接触させて積み
重ね、しかるのだ非酸化性雰囲気下への融点をこえる温
度にて多孔体に僅を含浸させることにより、セラミック
板または枠のメタライズ面とＣｕ−Ｗ、　Ｃｕ−Ｍｏ、
ｃｔｔ−ｗ−ｘ合金を一体化させてなる半導体搭載用複
合部品。 （２１Ｃａ−Ｗ、Ｃｕ−比、ＣＩＬ−Ｗ−ＭＯ合金にお
けるＷ、−１ｗ−ｈに対する侮の含有量が５〜２０重量
％であることを特徴とする特許請求の範囲第１項記載の
半導体搭載用複合部品。 ［３）　　Ｃｕ−Ｗ、Ｃｕ−Ｎｏ、Ｃｕ−Ｗ−１合金は
０．０２へ・２重量％のＮＬ、Ｆｅ、Ｃｏを含有してい
ることを特徴とする特ｒ＋請求の範囲第１項記載の半導
体搭載用複合部品。[Claims] (In a composite component for mounting a semiconductor using an alloy such as 11Ctt-W, Composite, or Go-W-1 as a heat dissipation substrate, a ceramic plate pre-metallized with a metal such as W or No. or the metallized surface of the frame and W, MO or W
- By stacking porous bodies obtained by firing 1% alloy powder in contact with each other, and impregnating the porous bodies with a small amount at a temperature exceeding the melting point in a non-oxidizing atmosphere, ceramic plates or frames can be formed. Metallized surface and Cu-W, Cu-Mo,
Composite parts for semiconductor mounting made by integrating ctt-w-x alloy. (21Ca-W, Cu-ratio, the semiconductor according to claim 1, characterized in that the content of W in the CIL-W-MO alloy, relative to -1w-h, is 5 to 20% by weight. Composite parts for mounting. [3] Cu-W, Cu-No, Cu-W-1 alloys contain 0.02 to 2% by weight of NL, Fe, and Co. Composite parts for mounting semiconductors as described in item 1.
JP10141483A 1983-06-06 1983-06-06 Composite component for loading semiconductor Granted JPS59225535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10141483A JPS59225535A (en) 1983-06-06 1983-06-06 Composite component for loading semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10141483A JPS59225535A (en) 1983-06-06 1983-06-06 Composite component for loading semiconductor

Publications (2)

Publication Number Publication Date
JPS59225535A true JPS59225535A (en) 1984-12-18
JPH0376579B2 JPH0376579B2 (en) 1991-12-05

Family

ID=14300044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10141483A Granted JPS59225535A (en) 1983-06-06 1983-06-06 Composite component for loading semiconductor

Country Status (1)

Country Link
JP (1) JPS59225535A (en)

Also Published As

Publication number Publication date
JPH0376579B2 (en) 1991-12-05

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