JPH0376579B2 - - Google Patents

Info

Publication number
JPH0376579B2
JPH0376579B2 JP58101414A JP10141483A JPH0376579B2 JP H0376579 B2 JPH0376579 B2 JP H0376579B2 JP 58101414 A JP58101414 A JP 58101414A JP 10141483 A JP10141483 A JP 10141483A JP H0376579 B2 JPH0376579 B2 JP H0376579B2
Authority
JP
Japan
Prior art keywords
alloy
frame
ceramic plate
ceramic
composite
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58101414A
Other languages
Japanese (ja)
Other versions
JPS59225535A (en
Inventor
Mitsuo Osada
Sogo Hase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP10141483A priority Critical patent/JPS59225535A/en
Publication of JPS59225535A publication Critical patent/JPS59225535A/en
Publication of JPH0376579B2 publication Critical patent/JPH0376579B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To obtain the title component at a low cost and high performance by a method wherein a ceramic plate or frame is brought to junction at the same time that Cu-W alloy is obtained in the process of impregnating Cu, when the alloy of cu-W, etc. is obtained by impregnation of Cu to a porous body of W, etc. CONSTITUTION:The ceramic plate or frame 12 having a metallized layer 13 and the porous body 11 of W, Mo, or W-Mo alloy are laminated, and Cu is impregnated thereto (process S) at a temperature over the melting point of Cu in a non-oxidizing atmosphere; thereby bringing both to junction with the Cu layer 14. As a result, the composite component having a thermal conductivity of the junction layer more excellent than that of the coventional component brazed with Ag solder and a low manufacturing cost. When the ratio of Cu in the component is 5-20wt% at this time, the rate of thermal epansion is kept in a range of 6-8(X10<-6>/ deg.C), which is approximate to the rate of expansion of ceramic at 6.5-7.5(X10<-6>/ deg.C), and accordingly the junction between the ceramic plate or frame and the Cu-W, Cu-Mo, and Cu-W-Mo becomes dense.

Description

【発明の詳細な説明】 この発明は製造コストが安価で熱伝導率のすぐ
れたCu−W、Cu−Mo、Cu−W−Moなどの複合
合金とセラミツク板または枠とを一体化させた半
導体搭載用複合部品の製造法に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a semiconductor that integrates a ceramic plate or frame with a composite alloy such as Cu-W, Cu-Mo, or Cu-W-Mo, which is inexpensive to manufacture and has excellent thermal conductivity. This invention relates to a method for manufacturing composite parts for mounting.

近年ICの演算速度の向上、トランジスタの電
気容量の増大、Ga−As、FETの出現等により、
半導体素子の駆動時に半導体素子に発生する熱を
いかに放熱させるかという点が大きな問題となつ
ている。
In recent years, due to improvements in the calculation speed of ICs, increases in the capacitance of transistors, and the appearance of Ga-As and FETs,
A major problem is how to dissipate the heat generated in a semiconductor element when the semiconductor element is driven.

半導体素子内に発生する熱は半導体素子が搭載
され、半導体素子裏面と接合された基板を通して
パツケージ外へ排出される。
Heat generated within the semiconductor element is discharged to the outside of the package through the substrate on which the semiconductor element is mounted and bonded to the back surface of the semiconductor element.

従つてこの基板材料には熱伝導度が高い材料を
用いるこが好ましい。
Therefore, it is preferable to use a material with high thermal conductivity for this substrate material.

ところで近年前記パツケージとしてセラミツク
を用いたセラミツクパツケージが多用されてい
る。このパツケージの場合、前記基板が電極取出
し用のセラミツク板または枠と一体化されてい
る。従つて基板材料としてAl2O3を主成分とする
磁器を使用する場合には、電極取り出し用のセラ
ミツク板または枠と一体焼成されるため問題ない
が、熱伝導性を向上させるためWやMoなど電極
取出し用のセラミツク板または枠と異種の材料を
基板材料として用いる場合、以下の如き問題が生
ずる。
Incidentally, in recent years, ceramic packages using ceramics have been frequently used as the packages. In this package, the substrate is integrated with a ceramic plate or frame for taking out the electrodes. Therefore, if porcelain containing Al 2 O 3 as the main component is used as the substrate material, there is no problem since it is fired integrally with the ceramic plate or frame for taking out the electrodes, but W or Mo is used to improve thermal conductivity. When a material different from the ceramic plate or frame for taking out the electrodes is used as the substrate material, the following problems occur.

即ちWやMo等を基板材料として用いた場合、
電極取出し用のセラミツク板(または枠)との接
合は通常銀ロウによるロウ付け方法が用いられ
る。
That is, when W, Mo, etc. are used as the substrate material,
For joining with a ceramic plate (or frame) for taking out the electrodes, a brazing method using silver solder is usually used.

この場合、WやMoなどはセラミツクとの熱膨
脹率の差が大きいため、ロウ付け工程における加
熱後の冷却時に熱歪によりセラミツク板または枠
が破損するとう問題が生ずる。
In this case, since W, Mo, and the like have a large difference in coefficient of thermal expansion from ceramic, a problem arises in that the ceramic plate or frame is damaged due to thermal distortion during cooling after heating in the brazing process.

このため、熱膨脹率がセラミツクと近いFe−
Ni合金またはFe−Ni−Co合金の薄板を基板とセ
ラミツク板または枠の間に介在させることが行な
われているが、かかる方法は熱伝導上好ましくな
い。
For this reason, Fe-
Although a thin plate of Ni alloy or Fe-Ni-Co alloy has been interposed between the substrate and the ceramic plate or frame, such a method is unfavorable in terms of heat conduction.

一方、熱伝導性が良く、熱膨脹率もセラミツク
または枠に近いBeOを用いることが考えられる
が、BeOは毒性を有するため、取扱いや製造が
困難であり、さらに入手にも問題がある。
On the other hand, it is possible to use BeO, which has good thermal conductivity and a coefficient of thermal expansion close to that of ceramic or frame, but BeO is toxic and difficult to handle and manufacture, and there are also problems in obtaining it.

本発明者らは、すでにかかる目的に適する熱伝
導度が高く、かつセラミツクと熱膨脹率の近似し
た材料としてW、MoまたはW−Moの合金粉末
の多孔体にCuを含浸して得るCu−W、Cu−Mo、
Cu−W−Mo複合合金を見出し、さらに特許出願
した(特願昭58−10790号、特願昭58−10791号)。
The present inventors have developed Cu-W, which is obtained by impregnating Cu into a porous body of W, Mo, or W-Mo alloy powder, as a material that has high thermal conductivity and has a coefficient of thermal expansion similar to that of ceramics and is suitable for such purposes. , Cu−Mo,
He discovered a Cu-W-Mo composite alloy and filed a patent application (Japanese Patent Application No. 10790/1982, Patent Application No. 10791/1983).

なお、これらCu−W、Cu−Mo、Cu−W−Mo
合金の製造法としてはW、MoまたはW−Mo合
金粉末を成形(プレスまたは押出し)し、これを
所定の空孔率を有する多孔体に焼成したのち、
Cuを含浸することにより、特性のより優れた材
料を得ることができることを見出し、さきに特許
出願した(特願昭58−17140号、58−17141号)。
In addition, these Cu-W, Cu-Mo, Cu-W-Mo
The method for manufacturing the alloy is to mold (press or extrude) W, Mo or W-Mo alloy powder, sinter it into a porous body with a predetermined porosity, and then
They discovered that a material with better properties could be obtained by impregnating it with Cu, and filed a patent application (Japanese Patent Application Nos. 17140 and 1982).

この発明は、W等の多孔体にCuを含浸してCu
−W等の合金を得る際に、このCuの含浸工程に
おいてセラミツク板または枠をCu−W合金を得
ると同時に接合することにより安価かつ高性能の
複合部品が得られることに着眼したものである。
In this invention, a porous material such as W is impregnated with Cu.
- When obtaining alloys such as W, we focused on the fact that inexpensive and high-performance composite parts can be obtained by joining ceramic plates or frames at the same time as obtaining the Cu-W alloy in the Cu impregnation process. .

通常Cu−W、Cu−MoあるいはCu−W−Mo合
金を放熱板として用いた半導体パツケージは第1
図aおよびbに示すような構造である。(Cu−W
合金の場合を例として示す。)即ち、1はCu−W
合板よりなる基板、2はパツケージ材であるセラ
ミツク枠である。そしてこのセラミツク枠2は
Cu−W合金基板1と接合される部分にメタライ
ズ層3が設けられ、このメタライズ層3とCu−
W合金基板1が銀ロウなどによつてロウ付けされ
ている。なお4は半導体素子、5はリードフレー
ム、6はボンデイングワイヤーである。
Normally, semiconductor packages using Cu-W, Cu-Mo or Cu-W-Mo alloy as a heat sink are the first
The structure is as shown in Figures a and b. (Cu-W
The case of alloy will be shown as an example. ) That is, 1 is Cu-W
The board is made of plywood, and 2 is a ceramic frame which is a package material. And this ceramic frame 2
A metallized layer 3 is provided at the part to be bonded to the Cu-W alloy substrate 1, and this metallized layer 3 and the Cu-W alloy substrate 1 are bonded to each other.
A W alloy substrate 1 is soldered with silver solder or the like. Note that 4 is a semiconductor element, 5 is a lead frame, and 6 is a bonding wire.

このような半導体パツケージを組立てる場合に
ついてのべると、第2図に示すように通常Cu−
W合金などの基板1とセラミツク枠または板2と
の接合は、セラミツク枠または板2にW、Moな
どを焼付けて形成したメタライズ層3とCu−W
合金等の基板1またはその上面のNiあるいはCu
のめつき面(図示せず)とを基板1上に銀ロウ7
をおいて積み重ねて加熱し、ロウ付けにて行なわ
れている。
When assembling such a semiconductor package, as shown in Figure 2, Cu-
The substrate 1 made of W alloy, etc., and the ceramic frame or plate 2 are bonded by using a metallized layer 3 formed by baking W, Mo, etc. onto the ceramic frame or plate 2, and Cu-W.
Ni or Cu on the substrate 1 such as alloy or its upper surface
Place the plating surface (not shown) on the substrate 1 with silver solder 7.
This is done by stacking them, heating them, and brazing them together.

この場合銀ロウ7としてはAgとCuの共晶合金
ロウが用いられることが多く、これは高価である
とともに熱伝導がよくないという欠点を有してい
る。
In this case, a eutectic alloy solder of Ag and Cu is often used as the silver solder 7, which has the drawbacks of being expensive and having poor thermal conductivity.

この発明は上記のような銀ロウによる基板とセ
ラミツク枠または板の接合の欠点を解消し、製造
コストが安価でかつ熱伝導のすぐれたCu−W等
複合合金放熱板とセラミツク枠または板よりなる
複合部品を提供しようとするものである。
This invention eliminates the disadvantages of bonding a substrate and a ceramic frame or plate using silver solder as described above, and provides a heat dissipating plate made of a composite alloy such as Cu-W and a ceramic frame or plate, which is inexpensive to manufacture and has excellent thermal conductivity. The aim is to provide composite parts.

以下この発明を第3図にもとづいて説明する。 This invention will be explained below based on FIG.

即ちこの発明は、予めメタライズしてメタライ
ズ層13を有するセラミツク板または枠12と
W、MoあるいはW−Mo合金の多孔体11を用
意し、このセラミツク板または枠11のメタライ
ズ層13と前記多孔体11を積層し、これに非酸
化雰囲気中でCuの融点をこえる温度にてCuを含
浸すること(工程S)により、Cu層14に両者
を接合するものであり従来の銀ロウによりロウ付
けされた複合部品に比べて接合層の熱伝導度がす
ぐれ、かつ製造コストが安価な複合部品が得られ
るのである。
That is, in the present invention, a ceramic plate or frame 12 having a metallized layer 13 which has been metallized in advance and a porous body 11 made of W, Mo or W-Mo alloy are prepared, and the metallized layer 13 of this ceramic plate or frame 11 and the porous body are prepared. 11 and impregnated with Cu at a temperature exceeding the melting point of Cu in a non-oxidizing atmosphere (step S), both are bonded to the Cu layer 14, which is not soldered with conventional silver solder. This makes it possible to obtain a composite part that has a bonding layer with superior thermal conductivity and is cheaper to manufacture than other composite parts.

なおこの発明において使用するセラミツク板ま
たは枠の材料としては、Al2O3、Si3N4、SiCある
いはこれらの複合セラミツクなど半導体パツケー
ジに使用されるものであればよく、特に限定され
ない。
The material for the ceramic plate or frame used in this invention is not particularly limited, and may be any material used for semiconductor packages, such as Al 2 O 3 , Si 3 N 4 , SiC, or composite ceramics thereof.

また、W、MoあるいはW−Mo合金などの多
孔体としては、本発明者らが既に特許出願した特
願昭58−15121、特願昭58−15122に記載の如く、
平均粒径1〜40μのW粉末、Mo粉末あるいはW
−Mo合金粉末に鉄族元素を0.02〜2重量%添加
した粉末を加圧成形後、非酸化性雰囲気で焼結し
た焼結多孔体であつて、これにCuを5〜20重量
%のCu含浸比率となるに適した空孔率を有する
ものがのぞましい。
In addition, as porous bodies such as W, Mo or W-Mo alloy, as described in Japanese Patent Application No. 58-15121 and Japanese Patent Application No. 58-15122, which the present inventors have already applied for,
W powder, Mo powder or W with an average particle size of 1 to 40μ
- A sintered porous body obtained by press-molding a Mo alloy powder containing 0.02 to 2% by weight of iron group elements and sintering it in a non-oxidizing atmosphere, and adding 5 to 20% by weight of Cu to this powder. It is desirable to have a porosity suitable for the impregnation ratio.

この発明にてCu−W、Cu−Mo、Cu−W−Mo
合金からなる半導体搭載用複合部品中のCu比を
5〜20重量%とするのは、熱膨脹率を6〜8(×
10-6/℃)の範囲に保たせるためであり、これは
セラミツクの熱膨脹率6.5〜7.5(×10-6/℃)に近
似させることによつてセラミツク板または枠と
Cu−W、Cu−Mo、Cu−W−Moとの接合に密に
するためである。
In this invention, Cu-W, Cu-Mo, Cu-W-Mo
Setting the Cu ratio in composite parts for mounting semiconductors made of alloys at 5 to 20% by weight requires a coefficient of thermal expansion of 6 to 8 (×
10 -6 /°C), and this is done by approximating the coefficient of thermal expansion of ceramic to 6.5 to 7.5 (x10 -6 /°C).
This is to ensure tight bonding with Cu-W, Cu-Mo, and Cu-W-Mo.

またこの発明において、複合部品中に鉄族元素
を0.02〜2重量%含有させるのは、W、Mo、W
−Mo粉末を焼成して焼結多孔体を得るに際し、
これらW、Mo、W−Mo粉末は融点が高いため
単独でその圧粉体を焼結する場合、所定の密度、
空孔率の焼結体を得ようとすると高温焼結が必要
である。
In addition, in this invention, the iron group elements contained in the composite part in an amount of 0.02 to 2% by weight include W, Mo, and W.
-When firing Mo powder to obtain a sintered porous body,
These W, Mo, and W-Mo powders have high melting points, so when sintering a green compact using them alone, the predetermined density,
In order to obtain a sintered body with high porosity, high temperature sintering is necessary.

ところが鉄族元素(Fe、Co、Ni)はタングス
テンと比較的低温で固溶体を作るため、W粉末、
Mo粉末、W−Mo粉末に微量の鉄族元素を添加
して焼結することにより、無添加の場合に比べて
大幅に低い温度で同一空孔率を持つ焼結多孔体が
得られるためである。
However, iron group elements (Fe, Co, Ni) form solid solutions with tungsten at relatively low temperatures, so W powder,
This is because by adding a small amount of iron group elements to Mo powder or W-Mo powder and sintering it, a sintered porous body with the same porosity can be obtained at a significantly lower temperature than when no additive is added. be.

そしてこのような効果のある鉄族元素の量を
0.02〜2重量%とするのは、0,.02重量%以下
では添加効果なく、また2重量%をこえるとCu
の含浸時Cu中への鉄族元素の固溶により熱伝導
度が低下するためである。
And the amount of iron group elements that have this effect
The amount of 0.02 to 2% by weight is 0.02 to 2% by weight. 02wt% or less, there is no addition effect, and if it exceeds 2wt%, Cu
This is because the thermal conductivity decreases due to solid solution of iron group elements in Cu during impregnation.

次にこの発明の製造法にて複合部品を得るに当
つての生産コスト面からの利点についてのべると
次の通リである。
Next, the advantages in terms of production costs in obtaining composite parts using the manufacturing method of the present invention are as follows.

即ち、従来のCu−W等複合合金放熱板とメタ
ライズ層を有するセラミツク板を銀ロウ付けする
場合には、この銀ロウ付けを容易にするために、
Cu−W等へのNi、Cuの表面処理工程あるいは銀
ロウ付け工程における加熱処理が必要であるが、
この発明においてはW、Mo、W−Mo多孔体と
メタライズ層を有するセラミツクス板または枠と
を積重ねてCuを含浸させるだけであるから、従
来法における銀ロウ付け接合に比べると、高価な
銀ロウ材を必要しないこと、従つて銀ロウ付けを
容易にするためのCu−W等への表面処理工程が
不要であること、など生産上の工程数をかなり減
ずることができ、生産コストの面で大きな利点を
有するのである。
That is, when silver brazing a conventional composite alloy heat sink such as Cu-W and a ceramic plate having a metallized layer, in order to facilitate this silver brazing,
Heat treatment is required in the Ni, Cu surface treatment process or silver brazing process on Cu-W, etc.
In this invention, W, Mo, and W-Mo porous bodies and ceramic plates or frames having metallized layers are simply stacked and impregnated with Cu. It is possible to significantly reduce the number of production steps, such as not requiring any additional material, and therefore not requiring a surface treatment process such as Cu-W to facilitate silver brazing, which reduces production costs. It has great advantages.

またこの発明の方法で得た複合部品の性能面で
の特徴は、銀ロウ付け層がないから複合部品の上
にSiなどの半導体素子を搭載する場合、銀ロウを
使用した場合に比べて熱伝導性のよいCuが接合
層に存在するために、半導体素子中で発生する熱
をパツケージ系外へ排出する場合に良好な特性を
示すのである。
In addition, the performance characteristics of the composite parts obtained by the method of this invention are that since there is no silver soldering layer, when semiconductor elements such as Si are mounted on the composite parts, the heat is lower than when using silver solder. Since Cu, which has good conductivity, is present in the bonding layer, it exhibits good characteristics when discharging heat generated in the semiconductor element outside the package system.

以下この発明を実施例により説明する。 This invention will be explained below with reference to Examples.

実施例 2〜3μのW粉末に粘結材として1重量%のカ
ンフアーを加え、これを30×30×1mmの大きさに
3t/cm2の圧力を加えて型押しした。次いでこの型
押体をH2ガス雰囲気中800℃で加熱してカンフア
ーを分解蒸発させたのち、H2ガス雰囲気中で
1500℃にて焼成し、Wの多孔体を得た。
Example: Add 1% by weight of camphor as a binder to 2-3 μm W powder, and make it into a size of 30 x 30 x 1 mm.
It was embossed by applying a pressure of 3t/cm 2 . Next, this embossed body was heated at 800°C in an H 2 gas atmosphere to decompose and evaporate the camphor, and then heated in an H 2 gas atmosphere.
A porous body of W was obtained by firing at 1500°C.

このW多孔体にWにて一面をメタライズした
Al2O3板のメタライズ面を合わせて積重ねたの
ち、H2ガス雰囲気中でこの積重ね状態のW多孔
体中にCuを含浸させ、メタライズ面にてCuによ
つて接合されたAl2O3とCu10%−W90%のCu−
W合金の複合体を得た。
One side of this W porous body was metalized with W.
After Al 2 O 3 plates are stacked with their metallized surfaces aligned, Cu is impregnated into the stacked W porous body in an H 2 gas atmosphere, and the Al 2 O 3 plates are bonded by Cu at the metallized surfaces. and Cu10%−W90%Cu−
A composite of W alloy was obtained.

かくして得られた複合体と予め調整した同一組
成のCu−W合金およびWでメタライズしたAl2O3
板をWのメタライズ面を介してAg−Cu共晶合金
ロウにてロウ付けした複合体について、接合面を
通し熱伝導性を測定したところこの発明により得
られた複合体は50%良好な熱伝導性を示した。
The composite thus obtained, a Cu-W alloy with the same composition prepared in advance, and Al 2 O 3 metallized with W
When we measured the thermal conductivity through the joint surface of a composite in which plates were brazed with Ag-Cu eutectic alloy solder through the metallized surface of W, we found that the composite obtained by this invention had a 50% better thermal conductivity. It showed conductivity.

【図面の簡単な説明】[Brief explanation of drawings]

第1図aおよびbは半導体パツケージの構造を
示す断面図、第2図は従来の銀ロウ付け方法によ
る複合体製造工程の説明図、第3図はこの発明の
方法で複合部品を得る工程説明図である。 11……W、MoあるいはW−Mo多孔体、1
2……セラミツク板または枠、13……メタライ
ズ層、14……Cu接合層。
Figures 1a and b are cross-sectional views showing the structure of a semiconductor package, Figure 2 is an explanatory diagram of the composite manufacturing process using the conventional silver brazing method, and Figure 3 is an illustration of the process of producing a composite component using the method of the present invention. It is a diagram. 11...W, Mo or W-Mo porous body, 1
2... Ceramic board or frame, 13... Metallized layer, 14... Cu bonding layer.

Claims (1)

【特許請求の範囲】 1 W、Moなどの金属にて予めメタライズした
セラミツク板または枠のメタライズ面とW、Mo
またはW−Mo合金粉末を焼成して得た多孔体を
接触させて積み重ね、しかるのち非酸化雰囲気下
Cuの融点をこえる温度にて多孔体にCuを含浸さ
せることによりセラミツク板または枠のメタライ
ズ面とCu−W、Cu−Mo、Cu−W−Mo合金を一
体化させることを特徴とする半導体搭載用複合部
品の製造法。 2 Cu−W、Cu−Mo、Cu−W−Mo合金におけ
るW、Mo、W−Moに対する含有量が5〜20重
量%であることを特徴とする特許請求の範囲第1
項記載の半導体搭載用複合部品の製造法。 3 Cu−W、Cu−Mo、Cu−W−Mo合金は0.02
〜2重量%のNi、FeCoを含有していることを特
徴とする特許請求の範囲第1項記載の半導体搭載
用複合部品の製造法。
[Claims] 1. The metallized surface of a ceramic plate or frame that is pre-metalized with metal such as W or Mo, and the
Alternatively, porous bodies obtained by firing W-Mo alloy powder are stacked in contact with each other, and then under a non-oxidizing atmosphere.
Semiconductor mounting characterized by integrating the metallized surface of a ceramic plate or frame with Cu-W, Cu-Mo, or Cu-W-Mo alloy by impregnating a porous body with Cu at a temperature exceeding the melting point of Cu. Manufacturing method for composite parts. 2 Claim 1, characterized in that the content of W, Mo, and W-Mo in the Cu-W, Cu-Mo, and Cu-W-Mo alloys is 5 to 20% by weight.
A method for manufacturing a composite component for mounting a semiconductor as described in . 3 Cu-W, Cu-Mo, Cu-W-Mo alloys are 0.02
2. The method for manufacturing a composite component for mounting a semiconductor according to claim 1, wherein the composite component contains up to 2% by weight of Ni and FeCo.
JP10141483A 1983-06-06 1983-06-06 Composite component for loading semiconductor Granted JPS59225535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10141483A JPS59225535A (en) 1983-06-06 1983-06-06 Composite component for loading semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10141483A JPS59225535A (en) 1983-06-06 1983-06-06 Composite component for loading semiconductor

Publications (2)

Publication Number Publication Date
JPS59225535A JPS59225535A (en) 1984-12-18
JPH0376579B2 true JPH0376579B2 (en) 1991-12-05

Family

ID=14300044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10141483A Granted JPS59225535A (en) 1983-06-06 1983-06-06 Composite component for loading semiconductor

Country Status (1)

Country Link
JP (1) JPS59225535A (en)

Also Published As

Publication number Publication date
JPS59225535A (en) 1984-12-18

Similar Documents

Publication Publication Date Title
US5981085A (en) Composite substrate for heat-generating semiconductor device and semiconductor apparatus using the same
US6238454B1 (en) Isotropic carbon/copper composites
US4663649A (en) SiC sintered body having metallized layer and production method thereof
JP2006505951A (en) Semiconductor substrate having copper / diamond composite material and method of manufacturing the same
JP3180622B2 (en) Power module substrate and method of manufacturing the same
JP2653703B2 (en) COMPOSITE MATERIALS, HEAT DISTRIBUTION MEMBER USING THE MATERIAL IN CIRCUIT SYSTEM, CIRCUIT SYSTEM, AND PROCESS FOR PRODUCING THEM
JP2001358266A (en) Material of heat radiation substrate for mounting semiconductor, method of manufacturing the same, and ceramic package using the same
JP4113971B2 (en) Low expansion material and manufacturing method thereof
JPH06268117A (en) Heat radiating substrate for semiconductor device and its manufacture
JPH05347469A (en) Ceramic circuit board
JPH08186204A (en) Heat sink and its manufacture
JPH022836B2 (en)
JPH0376579B2 (en)
JP3982111B2 (en) Semiconductor device member using ceramic and method for manufacturing the same
JP3695706B2 (en) Semiconductor package
JPH04348062A (en) Manufacture of heat-dissipating substrate for semiconductor mounting and package for semiconductor using the substrate
JPS6370545A (en) Semiconductor package
JP2751473B2 (en) High thermal conductive insulating substrate and method of manufacturing the same
JPS61121489A (en) Cu wiring sheet for manufacture of substrate
JP2967065B2 (en) Semiconductor module
JP2650044B2 (en) Connection structure between components for semiconductor devices
JP3559457B2 (en) Brazing material
JP2815656B2 (en) High-strength heat-radiating structural member for packaged semiconductor devices
JP2715686B2 (en) Method for manufacturing ceramic-metal joined body
JPH04168792A (en) Manufacture of high heat radiating ceramic circuit board with excellent thermal shock resistance