JPS59225356A - Speed detecting system - Google Patents

Abstract

PURPOSE:To enhance speed detecting speed over a total speed region, by calculating a speed by using the count value of a counter corresponding to a region to which an actual rotary speed belongs by counting a low speed clock pulse by a low speed counter while counting a high speed clock pulse by a high speed counter. CONSTITUTION:The pulse Pc generated from a rotary encoder 101 is subjected to wave form shaping by a wave form shaping circuit 102 to be converted to a pulse Pc' to be applied to a low speed cycle operating unit LSPU and a high speed cycle operating unit HSPU. On the other hand, the count value (n') of a counter 104' is transmitted to a second register 108'. A microprocessor 109 operates the cycle T of a pulse CT by using the numerical value (n') outputted from LSPU when s<=n and the numerical value (n) outputted from HSPU when s>n, a numerical value (s) is the boundary value of a high speed rotary region and a low speed rotary region. A rotary speed (v)(rpm) is outputted while operated by formula. In this case, P is the generation number of the pulse C generated per one rotation of the rotary encoder.

Description

[Detailed description of the invention] <Field of application in industry> The present invention relates to a speed detection method, and in particular, obtains the period of an output pulse train generated from a pulse generator attached to a servo motor, and uses the reciprocal of the period. This invention relates to a speed detection method for determining the actual speed of a servo motor.

<Prior Art> In controlling a servo motor such as a DC motor or an AC motor, the actual speed of the servo motor is detected, the difference between the actual speed and a command speed is calculated, and speed control is performed based on the difference. For this reason, various speed detection devices have been proposed in the past. FIG. 1 is a block diagram of a conventional speed detector capable of digitally detecting actual speed. In this conventional example, a Parnu coater (rotary encoder) 11 is installed.
, every time the motor rotates a predetermined amount, a pulse is generated from the PALNUCODER, and this pulse is sent to a counter 12K (force').
The contents of the counter are stored in register 1 at predetermined intervals.
The microcomputer 14 is made to read the contents of the data as the actual speed. Thereafter, the above operation is repeated to obtain the actual speed digitally.

However, with this conventional method, although it is possible to accurately detect the speed at high speeds, it is not possible to accurately detect the speed at low speeds because the pulse period generated from the Parnucoder increases. To increase the resolution at low speeds using the conventional method shown in Figure 1,
Either a) the number of pulses generated per revolution from the pulse generator 11 must be increased, or (b) the reading cycle must be lengthened. However, the number of pulses generated from the PALNUCODER 11 is limited to 10,000 pulses per rotation, and it is not possible to increase the resolution to this extent.

Therefore, the resolution cannot be increased by the former method (a).

- 10,000, the latter (b) means of lengthening the reading cycle deteriorates control responsiveness. That is, the read cycle of the register 16 by the microprocessor must be approximately υms (ms), and responsiveness cannot be improved.

For this reason, the applicant of this application uses high-speed clock pulses as a counter to measure the period of the output pulse train generated from the pulse generator attached to the servo motor! We have proposed a speed detection method in which the rotational speed of the servo motor is determined by calculating the inverse number of the hindlimb period by multiplying the number by 1.

<Disadvantages of Prior Art> By the way, in the speed detection method proposed above, the period of the output pulse is determined by having a counter count the clock pulses. In order to completely improve the detection accuracy during high-speed rotation with a short period, the frequency of the clock pulse must be increased. In other words, in the speed detection method proposed above, by increasing the frequency of the clock pulse, high-precision suction speed detection can be performed both during low-speed rotation and high-speed rotation.

However, if the frequency of the clock pulse is increased, the count value of the counter increases at low speeds, so the number of bits of the counter must be increased. Increasing the number of bits in the counter inevitably requires an expensive and highly functional microprocessor for calculating the speed from the period, and the processing time increases.

<Objective of the Invention> An object of the present invention is to provide a speed detection method that can digitally detect the speed of a servo motor at high speed and with high precision even during low speed rotation.

Another object of the present invention is to calculate the speed □ from the reciprocal of the period of the output pulse train.
To provide a speed detection method that does not require increasing the number of bits of a counter even when detecting speed.

<Summary of the Invention> The present invention has a counter that counts the period of an output caval array generated from a pulse generator attached to a servo motor, and a register that stores the counted period. In a speed detection method in which the rotational speed of the servo motor is determined by reading the period of the output pulse from the pulse generator that was input immediately before from the register and calculating the reciprocal of the period, a counter is used to count the period. A speed detection method in which a plurality of servo motors are provided, each uses a reno counter to count clock pulses of different frequencies, and the rotation speed of the servo motor is detected using the period counted by one of the counters depending on the rotation speed. According to this speed detection method, the speed can be detected with high accuracy even when rotating at a concave speed or when rotating at a high speed.

<Example> The number of clock pulses generated within one period of the pulse Pc output from the rotary encoder coupled to the shaft of the servo motor is 05.If the period of the clock pulse is ΔT, the period T and frequency f of the pulse Pc are as follows. respectively, T = n・Δ'J' (1)6
〇-0, J T (Hz/m”) (2)
It can be expressed as. Therefore, if the number of pulses Pc generated per rotation of the rotary encoder is P, then the rotational speed V of the servo motor can be calculated as follows.

From the above, in the present invention, the period T (-
n·ΔT) is determined, the reciprocal of the period is determined using a division instruction of the microprocessor, and the rotational speed V of the servo motor is calculated from equation (3) using the reciprocal. Then, a plurality of counters are provided to count the cycles, and the low-speed counter is made to count the low-speed clock pulses, and the high-speed counter is made to count the high-speed clock pulses. Alternatively, depending on which of the high-speed regions exists, the period T used for calculating equation (3) is selectively read out from either the low-speed counter or the high-speed counter, and the period T is used to calculate the calculation using equation (3). Calculating the speed.

FIG. 2 is a block diagram of the speed detection device according to the present invention, and FIG.
The figure is an explanatory diagram of waveforms at various parts in FIG. 2.

In FIG. 2, a rotary encoder 101 connected to the shaft of a servo motor (not shown) generates one pulse Pc for each predetermined rotation angle of the servo motor. /I/
LSPU (periodic calculation unit for low speed)
is applied to the high-speed periodic calculation unit H8PU. Note that the low-speed periodic calculation units (LS and PU) have exactly the same configuration as the high-speed periodic calculation unit (H8PU). Now, the pulse Pc is applied to S-4 type free lag flops (referred to as FF) 103 and 106' in the low-speed and high-speed periodic calculation units H8PU and LSP. FF103'-Taklock Exit Since it is configured to be set or reset in synchronization with the falling edge of HCP, this FF is configured to be set or reset in synchronization with the falling edge of HCP. Set. Also, F
Since the set output SET of F106 is coupled to the reset input terminal of the FF, the second high-speed clock
It is reset by the falling edge of I'S HCP.

In addition, FF10' is a low-speed clock obtained by frequency-dividing the high-speed clock/
Since the FF is configured to be set or reset in synchronization with the falling edge of CP, the FF is set or reset in synchronization with the falling edge of CP. Since the set output SET of the FF is coupled to the reset input terminal of the FF, it is reset by the fall 9 of the second low-speed clock pulse LCP.

Now, in the aid where FF103 is being reset,
Counter 104 counts high speed clock pulses HCP. Then, at a certain time h (see FIG. 3), when the waveform shaping circuit 102 generates /Cruz Pc', ii'
F103 is set to 1 by the pulse PC', and the counter 104 stops counting the high-speed clock pulse (HCP).Furthermore, the output of the AND gate 105 is set by the generation of the next high-speed clock pulse HCP. g+ 111, and the count value n of the counter 104 is shifted to the second register 108.At the same time, the FF 103 is reset again, and the counter 104 transfers its contents to the falling edge of the next high-speed clock/< Lunu HCP. After clearing to zero, the high speed clock pulse HCP starts counting again.

- On the other hand, a sampling pulse SP is generated at a predetermined period from a sampling pulse generator (not shown). ’” and the second register 108 is set to the second register 1.
The contents n of 08 are transferred.

On the other hand, in the low-speed periodic operation unit, the counter 104' counts the low-speed clock pulses LCP while the FFID filter' is reset. Then, when a pulse Pc' is generated from the waveform shaping circuit 102 at a certain time t1' (see FIG. 3), the FF 103'
', and the counter 104' stops counting the slow clock pulses LCP. Furthermore, upon generation of the next low-speed clock pulse LCP, the output of the AND gate 105' becomes "1", and the count value n' of the counter 104' is shifted to the luginutor 106'. Also, at the same time, F
F103' is reset again, and the counter 1G4' clears its contents to zero by the falling edge of the next low-speed clock pulse y-LCP, and then generates a low-speed clock pulse again to start counting CP.

On the other hand, the sampling pulse SP is a predetermined signal from a sampling pulse generator (not shown). When this sampling pulse SP is generated, the output of the AND gate 107' becomes 1' in synchronization with the falling edge of the low-speed clock pulse LCP9, and the second register 108' is stored in the second register 108'. The contents n' of ' are transferred.

The microprocessor 109 is connected to the second register 108°10.
When n and n' are shifted to 8', these n and n' are read and stored in a built-in general-purpose register Z, and the magnitude of n is determined from the numerical value S stored in the parameter memory 110. Note that the numerical value S is the boundary value between the high speed rotation area and the low speed rotation area, and the microprocessor 109 determines that the rotation speed of the servo motor is low if S≦n, and S>
If n, it is determined that the rotation speed of the servo motor is high.

If S≦n, a periodic calculation unit for low speed) L
The period of the pulse CP is calculated using the numerical value n' output from the SPU, or, if S>n, using the numerical value n output from the high-speed period calculation unit (H2PO). That is, if S≦n, set n'→γ and read the reciprocal 17TL of the period of the low-speed clock pulse LCP from the parameter memory 110, and 1. /TL→1/T8 (4
), and if n, n→γ, and read the reciprocal 1/T□ of the period of the high-speed clock pulse HCP from the parameter memory 110; 1. /T)
1 → 1/T, and execute the calculation of equation (4) to obtain 1/T-(1/TS)/γ (4) Pulse PC
Find the reciprocal 1/T of the period of '. If the reciprocal p 1//T is found by the calculation of the above formula, then the value 1//T stored in the parameter memory 110 (where P is 1 rotation of the rotary encoder) is calculated.
The rotational speed V (rpm) is calculated by calculating the rotation speed V (rpm) by using the number of pulses Pc generated in the rotational speed (number of pulses Pc generated).

In addition, in the above explanation, the speed region is divided into two regions, high speed rotation region and low speed rotation region, but the speed region is divided into 6 or more regions, and a periodic calculation unit is provided corresponding to each, and the actual speed is calculated. The actual speed may be calculated using the numerical value output from the first cycle calculation unit according to the speed region to which it belongs.

<Effects of the Invention> As explained above, according to the present invention, for example, two counters are provided for counting cycles, and the low-speed counter is configured to count low-speed clock pulses, and the high-speed counter is configured to count high-speed clock pulses. Depending on whether the actual rotational speed of the servo motor is in a low-speed region or a high-speed region, the speed is determined using the counted value of the counter according to the region to which the actual rotational speed belongs. The number of bits of the high-speed counter can be reduced, and an expensive and highly functional microprocessor is not required.

Highly accurate speed detection is possible over the entire speed range.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional speed detection device, FIG. 2 is a block diagram of a speed detection device according to the present invention, and FIG. 6 is an explanatory diagram of waveforms of various parts in FIG. 2. 101... Rotary encoder 102... Waveform shaping circuit 104, 104'... Counter 106.106. '108,108'...1st
and second register 109...microprocessor jlo...parameter memory H2PO...high-speed periodic operation unit LSPU...
・Low-speed periodic calculation unit FDV ... Frequency divider circuit patent applicant FANUC CORPORATION

Claims (2)

[Claims] (1) A counter that counts the period of an output pulse train generated from a pulse generator attached to a servo motor;
and a register for storing the counted period, and reads from the register the period of the output PALNU from the pulse generator inputted immediately before a certain sampling time,
In a speed detection method that calculates the rotational speed of a servo motor by calculating the reciprocal of the period, a plurality of counters are provided to count the period, and each counter is divided by a clock pulse of a different frequency. A speed detection method, characterized in that the rotation speed of a servo motor is detected using a period counted by one of the counters according to the rotation speed. (2) υ by a predetermined counter among the plurality of counters.
A patent characterized in that the magnitude of the uncounted period and a predetermined period is determined, and depending on the result, it is determined which counter uses the period counted to calculate the rotation speed. A speed detection method according to claim (1).