JPS59223860A - Fault diagnosis method of data processor - Google Patents

Fault diagnosis method of data processor

Info

Publication number
JPS59223860A
JPS59223860A JP58099774A JP9977483A JPS59223860A JP S59223860 A JPS59223860 A JP S59223860A JP 58099774 A JP58099774 A JP 58099774A JP 9977483 A JP9977483 A JP 9977483A JP S59223860 A JPS59223860 A JP S59223860A
Authority
JP
Japan
Prior art keywords
timer
interrupt
data processing
fault diagnosis
failure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58099774A
Other languages
Japanese (ja)
Other versions
JPS6342297B2 (en
Inventor
Keiji Maeda
前田 啓二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58099774A priority Critical patent/JPS59223860A/en
Publication of JPS59223860A publication Critical patent/JPS59223860A/en
Publication of JPS6342297B2 publication Critical patent/JPS6342297B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

PURPOSE:To eliminate the need for use of a special device by using an interruption controller and a timer to perform the fault diagnosis. CONSTITUTION:The prescribed initial values are set to timers 2 and 3 of a processor which counts the clock signals with reception of interruption. Then the contents of a counter are read with the next interruption. It is checked whether the counter contents are within a prescribed range of value. Then it is judged that a data processor has a fault when the counter contents are out of the prescribed range.

Description

【発明の詳細な説明】 この発明は、データ処理装置の故障診断方法に関し、特
に所定周期で割込みがかけられるデータ処理装置の故障
診断方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of diagnosing a failure of a data processing apparatus, and more particularly to a method of diagnosing a failure of a data processing apparatus in which an interrupt is applied at a predetermined period.

複雑な機能をもつデータ処理装置は、故障を発児するた
めの自己診断機能を備えるこ、とが不可欠となって来て
いる。従来の故障診断方法は、データ処理装置の一部を
なすマイクロプロセッサ基板自体は正常であるとの前提
のもとにこのマイクロプロセッサ基板を用いて当該装置
他の部分の故障診断を行なうものであった。
It has become essential for data processing devices with complex functions to have a self-diagnosis function to detect failures. Conventional fault diagnosis methods use the microprocessor board, which forms part of a data processing device, to diagnose other parts of the device on the assumption that the board itself is normal. Ta.

しかし、マイクロプロセッサ基板そのものは故障診断で
きないという欠点があった◇ この発明は、上記のような従来の問題点に鑑みてなされ
たものでタイマによシ発生させたプロセッサに対する定
期的な割込みを監視することによシ、装置全般にわたシ
自己診断を行なわせることができる故障診断方法を提供
することを目的とする。
However, the fault of the microprocessor board itself was that it could not be diagnosed. This invention was made in view of the above-mentioned conventional problems, and it monitors periodic interrupts to the processor that are generated by a timer. It is an object of the present invention to provide a fault diagnosis method that allows the entire device to perform self-diagnosis.

以下、この発明の一実施例を図について説明する。第1
図はこの発明の方法を実施したマイクロプロセッサ基板
のブロック図である。図示のように、々イクロプロセッ
サ1にはタイマ2.3及び割込コントローラ4がバス1
aを介して接続される。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a microprocessor board implementing the method of the invention. As shown in the figure, each microprocessor 1 has a timer 2.3 and an interrupt controller 4 connected to a bus 1.
connected via a.

第2図は第1図に示すマイクロプロセッサ1の動作を示
すメインプログラムのフローチャートである。処理P1
でマイクロプロセッサ1に内蔵されている割込カウンタ
NをOにセットし、処理P2でタイマ2に所定の値Y2
Iをセットし、処理P3で割込の禁止を解除する。これ
によシ、マイクロプロセッサ1は割込みを受付け、その
割込回数Nをカウントする。処理P4では次の割込みに
より、Nが所定数Mよシ大きいか否かの判断をし、82
Mであるならば処理5に進む・処理5では割込みを禁止
し、故障なしの処理をし、一連の故障診断処理を完了す
る。一方、82Mが成立しないとき、即ち割込回数Nが
所定数Mに達しないときは処理6に進みタイマ30カウ
ント値Y2を読込む。処理P7ではカウント値Y2と所
定の判定値Aとを比較し、A≦Y2のときは処理P4に
戻る。
FIG. 2 is a flowchart of a main program showing the operation of the microprocessor 1 shown in FIG. Processing P1
In step P2, interrupt counter N built in microprocessor 1 is set to O, and in process P2, timer 2 is set to a predetermined value Y2.
I is set, and the prohibition of interrupts is canceled in process P3. Accordingly, the microprocessor 1 accepts the interrupt and counts the number of interrupts N. In process P4, it is determined whether N is larger than a predetermined number M by the next interrupt, and 82
If it is M, proceed to process 5. In process 5, interrupts are prohibited, processing is performed without failure, and a series of failure diagnosis processes is completed. On the other hand, if 82M is not satisfied, that is, if the number of interrupts N does not reach the predetermined number M, the process proceeds to step 6 and reads the timer 30 count value Y2. In process P7, the count value Y2 is compared with a predetermined judgment value A, and when A≦Y2, the process returns to process P4.

A≦Y2でないとき、即ち少なくともタイマ2が判定値
Aまでカウントする時間内に割込みの発生回数がM回以
上にならなかったときは、装置に異常があるものとし、
処理P8によ、シ故障表示をする。
When A≦Y2, that is, when the number of interrupts does not exceed M times within the time period for timer 2 to count up to the judgment value A, it is assumed that there is an abnormality in the device;
According to process P8, a failure is displayed.

第3図は割込処理のフローチャートである。処理PIO
によシ、割込カウンタのNIJ″−0であるが否かを判
断をする。N=00ときは処理11に進み、割込カウン
タ+1をする。処理P12ではタイマ3にY3Iの設定
をし、当刻割込処理を終了する。一方、処理10でN’
tOと判断されたときは処理13に進み、タイマ30カ
ウント値Y3を読込む。処理14において、X≧Y3≧
2の判断をし、イエスのときは処理11に進み、ノーの
ときは処理15に進み、故障の表示は、Y3がX及びY
で定められる範囲にカウント値Y3が存在せず、装置に
異常があることを表示するものである。
FIG. 3 is a flowchart of interrupt processing. Processing PIO
Then, it is determined whether the interrupt counter is NIJ''-0 or not. If N=00, the process advances to process 11 and the interrupt counter is incremented by 1. In process P12, timer 3 is set to Y3I. , ends the current interrupt process.Meanwhile, in process 10, N'
When it is determined that it is tO, the process advances to step 13 and reads the timer 30 count value Y3. In process 14, X≧Y3≧
2, if yes, proceed to process 11, if no, proceed to process 15, and the malfunction indication is that Y3 is X and Y
This indicates that the count value Y3 does not exist within the range defined by , and that there is an abnormality in the device.

第4回は、以上のように構成されたプログラムの下でb
に示されるような一定期Tを持った割込要求信号を割込
コントローラ4へ供給した場合タイマ2,3及び割込カ
ウンタの変化状態を表わすタイミングチャートであシ、
横軸に時間tを縦軸に夫にのカウント値をとっている。
In the fourth session, b. under the program configured as above.
A timing chart showing the changing states of timers 2 and 3 and the interrupt counter when an interrupt request signal with a fixed period T as shown in FIG.
The horizontal axis shows time t, and the vertical axis shows the husband's count value.

ただし、割込Hbに示される割込コントローラ4から出
力される信号の立ち上ル時点でなされるものとする。
However, it is assumed that this is done at the rising edge of the signal output from the interrupt controller 4 indicated by the interrupt Hb.

第4図Cに示すように、時刻toでメインプログラムの
処理P2(タイマ2の設定)が実行されると、タイマ2
のカウント値Y2は、カウントの進行によシ、即ち時間
と共に一定の傾きをもって減少していく。時刻t1iで
は、割込に基づく、タイマ3の設定が実行されていない
ため、第4図aに破線で示すようにタイマ3のカウ゛ン
ト値Y3は不定である。時刻t1で割込コントローラ4
の信号が立ち上るので、割込がかけられ、タイマ30カ
ウント値Y3はaに示されるようにある値Y3工に設定
される。その彼、クロック信号をカウントすることによ
シ、時間と共に一定の傾きをもって減少していく。dは
割込カウンタのNを示す。
As shown in FIG. 4C, when processing P2 (setting of timer 2) of the main program is executed at time to, timer 2
The count value Y2 decreases with a constant slope as the count progresses, that is, with time. At time t1i, the setting of the timer 3 based on the interrupt has not been executed, so the count value Y3 of the timer 3 is indeterminate, as shown by the broken line in FIG. 4a. Interrupt controller 4 at time t1
Since the signal rises, an interrupt is generated, and the timer 30 count value Y3 is set to a certain value Y3, as shown in a. By counting the clock signal, it decreases with a constant slope over time. d indicates N of the interrupt counter.

しかる後、時刻t2において再度割込がかけられると、
マイクロプロセッサ1はこれに応答してその時点のタイ
マ30カウント値Y3を読取シ、所定の設定値X、zと
比較する。カウント値Y3に対して X≦Y3≦2 が成立する場合は、装置は正常に機能しているものとし
て、再び値73Iをタイマ3に設定し、以上説明の動作
を反俵する。従って、タイマ3の内容は、aで示される
ような変化をする。しかるに、bに示すように、周期的
な割込がなされているにも拘らず、割込が不規則に実行
され、タイマ30カウント値Y3が Y3<X 又は y a (Z となってしまった場合、即ち第5図で示されるように X≦Y3≦2 の範囲外となってしまっている場合は、割込処理機能に
故障があると判断し、第3図の処理15によシ故障を表
示する。
After that, when another interrupt is applied at time t2,
In response, the microprocessor 1 reads the current count value Y3 of the timer 30 and compares it with predetermined set values X and z. If X≦Y3≦2 holds for the count value Y3, it is assumed that the device is functioning normally, and the value 73I is set in the timer 3 again, and the operation described above is repeated. Therefore, the contents of timer 3 change as shown by a. However, as shown in b, even though periodic interrupts are performed, the interrupts are executed irregularly, and the timer 30 count value Y3 becomes Y3<X or y a (Z In other words, if it is outside the range of X≦Y3≦2 as shown in FIG. Display.

以上のように、この発明によれば、割込コントローラ及
びタイマーを用いて故障診断を行なっているために特別
な装置を必要とすることなく、シかも充分な故障自己診
断結果を得られると云う効果がある。
As described above, according to the present invention, since fault diagnosis is performed using an interrupt controller and a timer, sufficient fault self-diagnosis results can be obtained without the need for special equipment. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はマイクロプロセッサ基板の構成を示す構成図、
第2図はメインプログラムのフローチャー)、第3図は
割込処理プログラムのフローチャート、第4図は装置に
故障がない時の各部の状態を示すタイミングチャート、
第5図は装置に故障があったときの各部分の状態を示す
タイミングチャートである。 1・・・マイクロプロセッサ、2,3・・・タイマ、4
・・・割込コントローラ。 代理人 大岩増雄 fiS   生  図 手続補正書(自発〕 11.、(オD5す1.10層1−1 特許庁長官殿 ]、事件の表示   特願昭58−99774号2、発
明の名称 データ処理装置の故障診断方法 3、補正をする者 代表者片山仁へ部 4、代理人 5、補正の対象 明細書の発明の詳細な説明の憫 6、補正の内容 (1)明細書第3頁第9行目「N5Mであるならば処理
5に進む。処理5では割」とあるのを「N5Mであるな
らば処理P5に進む。処理P5では割」と補正する。 (2)明細書第3負第13行目「は処理6に進み」とあ
るのなrij処理処理圧6み」と補正する。 131明細書第4頁第3行目「N=0のときは処理11
に進」とあるの&rN=0のときは処理P11に進」と
補正する。 以上
Figure 1 is a configuration diagram showing the configuration of a microprocessor board;
Figure 2 is a flowchart of the main program), Figure 3 is a flowchart of the interrupt processing program, Figure 4 is a timing chart showing the status of each part when there is no failure in the device,
FIG. 5 is a timing chart showing the state of each part when there is a failure in the device. 1... Microprocessor, 2, 3... Timer, 4
...Interrupt controller. Agent: Masuo Oiwa fiS Draft drawing procedure amendment (spontaneous) 11. (D5S1.10 layer 1-1 Mr. Commissioner of the Japan Patent Office), Indication of case: Japanese Patent Application No. 58-99774 2, Name of Invention Data Processing Device failure diagnosis method 3, Representative Hitoshi Katayama of the person making the amendment, Department 4, Agent 5, Detailed explanation of the invention in the specification to be amended 6, Contents of the amendment (1) Page 3 of the specification In the 9th line, "If N5M, proceed to process 5. Process 5 is a discount" is corrected to "If N5M, proceed to process P5. Process P5 is a discount." (2) Specification No. 3 Negative 13th line ``Proceed to process 6'' is corrected to ``Rij processing pressure 6''. 131 Specification, page 4, 3rd line ``If N=0, proceed to process 11.''
``Proceed to process P11 when &rN=0'' is corrected. that's all

Claims (1)

【特許請求の範囲】[Claims] 所定周期で入力される割込みを受付けるようにしたプロ
セッサを有するデータ処理装置の故障診断方法において
、割込みの受付けによシクロツク信号をカウントする上
記プロセッサのタイマに所定の初期値をセットし、次の
割込みによシ上記カウンタの内容を読み込み、上記内容
が所定範囲の数であるか否かをチェックして上記所定範
囲外のときはデータ処理装置に故障があると判断をする
ようにしたことを%徴とするデータ処理装置の故障診断
方法。
In a fault diagnosis method for a data processing device having a processor configured to accept interrupts input at a predetermined period, a predetermined initial value is set in a timer of the processor that counts cyclic signals upon acceptance of an interrupt, and the next interrupt is The content of the above counter is read, and it is checked whether the above content is within a predetermined range, and if it is outside the predetermined range, it is determined that there is a failure in the data processing device. A method of diagnosing a failure of a data processing device based on the characteristics of the data processing device.
JP58099774A 1983-06-02 1983-06-02 Fault diagnosis method of data processor Granted JPS59223860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58099774A JPS59223860A (en) 1983-06-02 1983-06-02 Fault diagnosis method of data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58099774A JPS59223860A (en) 1983-06-02 1983-06-02 Fault diagnosis method of data processor

Publications (2)

Publication Number Publication Date
JPS59223860A true JPS59223860A (en) 1984-12-15
JPS6342297B2 JPS6342297B2 (en) 1988-08-23

Family

ID=14256302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58099774A Granted JPS59223860A (en) 1983-06-02 1983-06-02 Fault diagnosis method of data processor

Country Status (1)

Country Link
JP (1) JPS59223860A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63221437A (en) * 1987-03-11 1988-09-14 Alps Electric Co Ltd Detecting system for cpu runaway

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02109490U (en) * 1989-02-21 1990-08-31

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5592951A (en) * 1978-12-29 1980-07-14 Fujitsu Ltd Automatic reset unit for out-of-control state of microprocessor
JPS57134757A (en) * 1981-02-12 1982-08-20 Matsushita Electric Ind Co Ltd Self-diagnosis system for microcomputer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5592951A (en) * 1978-12-29 1980-07-14 Fujitsu Ltd Automatic reset unit for out-of-control state of microprocessor
JPS57134757A (en) * 1981-02-12 1982-08-20 Matsushita Electric Ind Co Ltd Self-diagnosis system for microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63221437A (en) * 1987-03-11 1988-09-14 Alps Electric Co Ltd Detecting system for cpu runaway

Also Published As

Publication number Publication date
JPS6342297B2 (en) 1988-08-23

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