JPS59222093A - 2-phase ac motor drive device - Google Patents

Abstract

PURPOSE:To rotate steplessly a motor from a low speed to a high speed by providing a 2-phase signal generator which outputs a sine wave signal and a cosine wave signal to vary the frequency of a clock. CONSTITUTION:A 2-phase signal generator 1 which has an up-down counter 11 for counting a normal rotation clock or a reverse rotation clock and a memory circuit 12 for outputting a sin wave signal and a cos wave signal by the output of the counter is provided. According to this, a motor can be rotated steplessly from a low speed to a high speed by altering the frequency of the clock, and since the waveform of the drive signal is sin wave and cos wave, the rotation can be made extremely smooth.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive device for a two-phase AC motor, and more specifically, the present invention relates to a drive device for a two-phase AC motor, and more specifically, it is a two-phase AC motor drive device that uses a sine wave whose phase is 90° different from a positive phase and a co-wave.
The present invention relates to a dual sum alternating current motor drive device that smoothly drives a paper feed motor of a recorder using a circuit that generates s-waves.

Generally, when direct current is used as a drive source signal for a motor, this direct current is converted to alternating current using, for example, a V/F conversion circuit or an O1 variable reactance oscillator circuit, and then a two-phase signal is obtained using a phase shift circuit or the like. ing. In this case, in order to make the motor rotate smoothly, the phase difference between the two signals should be adjusted to exactly 90°, and the waveform should be as sine wave or co-wave as possible.
These adjustments were not easy and led to the complexity of the device.

This invention was made in view of the following two points, and its purpose is to provide a memory circuit that stores quantized digital values of sin and cos, and an up/down counter that retrieves the stored values in time series. To provide a two-phase AC motor drive device which is equipped with a combined two-phase reliable generation circuit, has no uneven rotation from low speed to high speed, and can easily perform forward and reverse rotation.

Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the accompanying drawings.

Referring to FIG. 1, this drive device has an input terminal A
For example, if a forward rotation clock is added to -.

Or if, for example, a reverse clock is applied to terminal B,
For both of them, it has a two-phase signal generation circuit 1 that generates two-phase digital signals (t7) of sine waves and cosine waves,
One of the above s output from this two-phase signal generation circuit 1
The i n-wave signal is transmitted to each first latch circuit 2 and D/
Two-phase AC motor 5 via A converter 3 and amplifier circuit 4
is applied to one excitation coil, and the other co
Similarly, the s-wave signal is transmitted to each second launch circuit 6 and [
] /Δ converter 7 and amplifier circuit 8 so as to be applied to the other excitation coil of the two-sum AC motor 5 .

In this @ case, switching between the forward clock and the reverse clock is to convert a single clock signal (not shown) into the forward clock or reverse clock via the gate I-circuit, which can be operated manually or electrically. controlled by physical means.

The above-mentioned two-phase signal generation circuit 1 includes an up/down counter 1 which counts R1 clock signals manually inputted from a terminal A or a terminal B, and a counter 11 which outputs a s i n wave signal and a cosine wave output. It has a memory circuit I2 at an address corresponding to a different numerical value of J, which stores digital values quantized with a resolution of, for example, 8 bits I.
The respective sin wave signals and c and o s wave signals are as follows.
According to the division signal from the up/down counter 11,
The information is output alternately and in chronological order. That is, in a register provided in the memory circuit 12 and extending from the LSB address (not shown), that is, the O address to the MS'B address, for example, a sine wave signal is stored at the even address, and a cosine wave signal, for example, is stored at the odd address. Signals are stored respectively, and each of these addresses is sequentially scanned by the 81 number output from the knob down counter 11.

In this case, one of the two signals outputted from the -J2 storage circuit 12, for example, a sin wave signal, is sent to the first launch circuit 2, and a cosine wave signal is sent to, for example, the second latch circuit. A control circuit 13 is provided so that the signals are distributed and input to the respective channels. If the LSB of the up/down counter 11 is O, for example, the control circuit 13 sends out a reset pulse to the first launch circuit 2 to input a sin wave signal, and if the LSB of the up/down counter 11 is For example, if it is 1, the second latch circuit 6 sends out a low pulse and inputs a cosine wave signal.

In this embodiment, a cell 1 for setting the upper limit count value of the up-down counter 11, corresponding to the number of addresses of registers provided in the memory circuit 12, is provided.
- A circuit 14 and its reset circuit 5 are provided. For this reason, when a normal rotation clock is input, an up-run is repeated from the O address to the MSB number.
When the jφ rotation clock is inputted at 4, the counting direction is reversed and a down count towards address 0 is started. When this number reaches address 0, the down-count 1~ is performed again from the MSB address to address 0, and this division operation is repeated while the reverse clock is input. In addition,
This reset circuit is necessary, for example, when using an up/down counter to 8 pins 1 in 200 base, etc. In the case of 8 pin I, it is 25 G base, and it is also decomposed into 25 G in the storage means. It is clear that this is unnecessary if it has a fixed take.

-1- The latch circuit 2 of the memory 1 includes a gate circuit on the input side, and when it receives a latch pulse from the control circuit 13 indicated in "2", the latch circuit 2 of the memory 1 is sequentially sent out from the memory circuit 12 indicated in "2".
Only the sine wave signal among the n wave signal and the cos wave signal is selectively inputted, and this is temporarily held until the next s i r+ signal is sent out, and is then stored in the -1 and memory 1 of the next stage. D/A
It is sent to the converter 3. ”2 memory 1 D/
The A converter 3 converts an 8-pin 1-configured Sl "1-wave signal into an analog wave, and this converted sine-wave signal is sent to the above-mentioned two-phase AC motor via the amplifier circuit 4 with two memories 1. is added to the corresponding excitation coil.

A circuit similar to that described above is also configured for the path of the CO8 wave signal. That is, the second latch circuit 6 and the second
A D/A converter 7 and a second amplifying circuit 8 are provided, and the output of the amplifying circuit of the second memory 2 is applied to the corresponding excitation coil of the two-phase AC motor 5. Note that the first and second D/A converters 3 and 7 are provided with a reference value circuit 16 for applying a reference voltage and timing pulse for D/A conversion.

Next, the operation of this drive device will be explained with reference to FIG. 2. The memory circuit 11 has Q as shown in (a).
There are a total of F, i n -1-] registers from the address n@, and the digital values So to Sm of the sin wave signal are stored in the even addresses, and the digital value Go of the cos wave signal is stored in the even address. to Crn are stored at odd addresses. Therefore, for example, if SO or Co is a value of 0°, and Sm or Cm is a value of 359°, and the values are stored every 1°, the total number of addresses n will be 720. The frequency of the black mark shown in (b) is such that one revolution of the motor scans from address Q to address n.
The speed is set by a speed setting device in proportion to the motor rotation speed calculated from the paper feed speed in step 1. When this clock is multiplied by a1 by the up/down counter 11 and inputted to the storage circuit 12, the multiples of the clock are sequentially scanned at each address and the stored s i n wave signal and COS wave signal are alternately Output. The control circuit 13 synchronizes with the sending timing of the number signal output from the up/down counter.
Latch signal for holding the in-wave signal ((c) in the same figure)
and a latch signal for holding the cos wave signal (the same figure (
D)) is sent to the corresponding first and second latch circuits 2 and 6. As a result, the first and second latch circuits 2
, 6, sin to 8 pits 1 shown in (po) and (to)
A wave signal and a cos wave signal are sent out, and these signals are
and (1-) in the second D/A converters 3 and 7, respectively.

It is converted into an analog sin wave signal and a CO8 wave signal as shown in (h).

In this case, assuming that the forward rotation clock is input from the Q address to the address (Q-1,), and the switch is made to the φ rotation lock from the Q address, the amplifier town counter 11 performs the subtraction H1 number. Even if the temporal timing is the same as the forward rotation clock, the address scan is backward. In other words, as related to (G) and (H), the subsequent conversion output from the sine wave signal Sk stored in address Q is (Sk-1), (S
k-C)..., and the cos wave signal is (Ck-+)
, (cl(-2)...what's going on? I mean, this Q
90° of sine wave signal and COS wave signal at 1n address border
Assuming that the phase difference between the two rotations is reversed, and the motor rotation is normal rotation as shown in (S) at the time before the Q address, for example, it is reverse rotation from the 12th address onwards.

Note that the two-phase signal generating circuit 1 can also be configured by a microcomputer or the like. Here &, for example, up/down counter 11, note 1. α circuit 12, control circuit 13
, each function of the set circuit 14 and the reset circuit 15 is performed by the Progera 11 counter, ■? ,(1) M,Microprocessor,R,A IνIA! All you have to do is change to r directly.

An example of the operation when configured with a microcomputer is shown in Fig. 3, but to explain its outline, it is inputted at the start and "C is turned to up/down 1 (forward rotation) or town clock 1". If the counter is 1-, it is further determined whether it is address MS1-3.If M S + < address, l = S B address (receive 1 to address 0, and an even number of tears, Depending on the odd number, the corresponding launch pulse is sent out and the ROM is
Sort the s i n wave signal and cos wave signal values read from . If there is no MSB address, move up 1-up, then sort it in the same way each time, and
If you repeat this to address sr3 or address 13, the motor will continue to rotate in the forward direction.

) If the L roll lock is manually applied to IIJ, the judgment as to whether to go to Anobu Count 1 is NO, so as shown on the right side of the figure, count down from MS 13 to SB address. , the signals read from the ROM are similarly sorted depending on whether the a1 value is an even number or an odd number.

As described above in detail, the dual-sum AC motor drive device according to the present invention includes an up-down counter that counts a1 the forward rotation clock or reverse rotation clock for driving the motor, and a sine wave signal generated by the output from the up-down counter. The two-phase signal generation circuit includes a memory circuit configured to distribute and output cosine wave signals and a storage circuit for distributing and outputting cosine wave signals.

According to this drive device, the motor can be rotated steplessly from low speed to high speed by changing the clock frequency, and since the waveforms of the drive signal are sin waves and cos waves, the rotation is extremely smooth. be.

Also, the forward and reverse rotation of the motor is determined by the up/down counter 1.
It can be easily controlled by simply switching between the forward rotation clock and the reverse rotation clock input to the input terminal 1, and does not require a complicated circuit like the conventional one. Therefore, there are few adjustment points, and the adjustment can be performed relatively easily.

[Brief explanation of drawings]

The attached drawings all relate to an embodiment of the two-phase motor drive device according to the present invention, and FIG. 1 is a block diagram thereof, FIG. 2 is a timing chart of each signal, and FIG. 3 is an implementation example shown in FIG. 1. This is a flowchart 1- of signal processing when a microcomputer is applied to the two-phase signal generation circuit in the example. In the figure, ■ is a two-phase phase generation circuit, 2 and 6 are latch circuits, and 3
, 7 are D/A converters, 4 and 8 are amplifier circuits, 5 is a two-phase AC motor, 11 is an up/down counter, 12 is a memory circuit, and 13 is a control circuit. Patent Applicant Hioki Electric Co., Ltd. Agent Patent Attorney Takuya Ohara (procedure amendment band motion) 1. Indication of the case 1981 Patent Application No. 97680 2 Name of the invention 2-phase AC motor drive device 3 Person making the amendment Relationship to the case Patent applicant 6249 Sakaki, Sakaki-cho, Hanishina-gun, Nagano Prefecture Hioki Electric Co., Ltd. Representative Tsunei Hioki 5, Date of amendment order Procedure amendment (voluntary) 1, Indication of the case 1982 Patent Application No. 97680 2, Name of the invention 2-phase AC motor drive device 3, Person making the amendment Case Relationship with Patent Applicant Representative Tsunei Hioki 5, Date of Amendment Order 7, Contents of Amendment (1) Particularly '1 Claims are amended as shown in the attached sheet. (2) Specification, line 600, line 1 r 1. , S B
In front of J, add "1 of H11 signal. (3) F up/down counter on line 19 of the same page" [
"Correct it as up/down counter J. (4) Book II, page 7, line 8 to the next line r
``sin signal'' is corrected to lt' sin wave signal January. (5) On the 19th line of the same page, "Width circuit 8" is corrected to "Width circuit 8 is J." (6) In the specification, on the 6th line of page 8, "Memory circuit 11" is corrected. (7) On the 14th line of the same page, the statement "The total number of addresses is 11" should be corrected as "Memory circuit 1.2.!l."
The total number of addresses is corrected to j. (8) In the specification, page 11, line 4: “(O @ ground...J
Correct the statement to read ``Uf'' (address O). Attachment above (Japanese Patent Application No. 58-97680) ``2. Claims Single-phase tarok signals whose phases differ by 90 degrees from each other 2.
In a two-phase AC motor drive device that forms AC signals of different phases and adds the two signals to corresponding excitation coils of a two-phase AC motor to drive the two-phase AC motor, the clock signal consists of a forward rotation clock and a reverse rotation clock, an up/down counter that adds or subtracts the number of phases corresponding to either one of the input tally signals and outputs the H1 value as an address signal; The first and second register groups each store a quantized digital value so that the signal of the other phase changes in proportion to the sine wave in an interval of 2π to 2π radians, and the signal of the other phase changes in proportion to the cosine wave. a memory circuit in which the first and second register groups are alternately scanned by the address signal from the up-down counter and sequentially outputs the stored values in IL; and the address signal from the amplifier-down counter. 6.4 A signal for distributing to the first or second register group of the memory circuit and a first or second register group output from the memory circuit.
a two-phase phase generation circuit configured to include a signal for selectively manually inputting the digital values of the register groups to the first and second D/A converters each including a launch circuit; have,

Claims (1)

[Claims] Single-phase clock signals whose phases differ by 90°2
A two-phase AC motor drive device that forms AC signals of different phases and adds the two signals to corresponding excitation coils of a two-phase AC motor to drive the motor. The clock signal consists of a forward rotation clock and a reverse clock, and an up/down counter that performs addition or calculation according to one of the input clock signals and outputs the divided value as an address signal. Among the two-phase signals, one phase signal changes in an interval of O to 2π radians in proportion to a sine wave. The signal of the other phase has first and second register groups each storing a quantized digital value such that the signal changes in proportion to a cosine wave, and the first and second register groups each store a quantized digital value. is alternately scanned by the address signal from the amplifier down counter and sequentially outputs the stored values; and the address signal from the up/down counter is sent to a first or second register group of the storage circuit. A signal for distributing and 1) selectively inputting the digital values of the first or second register group output from the storage circuit to the first and second D/A converters each including a latch circuit; a two-phase signal generating circuit configured to include a control circuit for transmitting a signal to cause the analog output to increase, and a control circuit for transmitting a signal to cause the analog output to increase. A two-phase AC motor drive circuit, characterized in that it is applied to a corresponding excitation coil of the motor.