JPH0532923B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a digital sine wave generator that outputs sine wave digital data based on a clock signal.

"Prior Art" Conventional digital sine wave generators generally include an oscillator, a ROM, and a D/A converter. At this time, a commercially available ROM is used, and its power supply voltage is 5V.

Additionally, in general, when sine waves are synthesized without using a ROM, it is difficult to obtain a sine wave with a low distortion rate due to poor resolution.

"Problem to be Solved by the Invention" However, in such a conventional digital sine wave generator, if the power supply voltage of the ROM is different from the power supply voltage of the oscillator operational amplifier or the C-MOS of the D/A converter, In this case, it is necessary to insert an interface between the ROM and the operational amplifier, etc., which complicates the configuration and increases the cost.
When the voltage was set to 5V, there was a problem in that the noise margin became small, causing malfunctions and hindering the generation of the desired sine wave.

The present invention has been made in view of these conventional problems, and provides a digital sine wave generator that can reliably obtain a desired sine wave with a simple configuration and low cost. The purpose is to

"Means for Solving the Problems" The gist of the present invention to achieve the above object is as follows: 1. Generate two or more types of pulses with different frequencies based on a clock signal from an oscillator, and generate half a sine wave pulse. dividing the cycle into a plurality of sections corresponding to various types of pulses, dividing the half cycle into two into an addition section and a subtraction section, and adding up the number of pulses generated in each section in the addition section; a digital circuit that generates an addition signal as a signal and a subtraction signal as a signal for subtracting the number of pulses in the subtraction area; and calculating the number of pulses based on the addition signal and the subtraction signal. A digital type comprising: an up-down counter that outputs a group of digital data corresponding to the waveform of the half cycle by adding or subtracting; and a D/A converter that converts the group of digital data into an analog value. Sine wave generator.

2. The digital sine wave generator according to item 1, wherein the sign of the analog value is reversed to obtain an analog value of a half cycle opposite to the half cycle of the sine wave.

3. The digital sine wave generator according to item 2, wherein one cycle of the sine wave is constituted by an analog value of a half cycle of the sine wave and an analog value of a half cycle opposite to the half cycle. exists in

"Operation" The digital circuit generates various pulses with different frequencies according to each section of the half cycle, and generates an addition signal in the addition section that divides the half cycle into two, and a subtraction signal in the subtraction section. Occur.

The up-down counter adds pulses while the addition signal is being generated, and the successively added values become the digital data at that point. When a subtraction signal is generated, the number of generated pulses is successively subtracted from the added value, and the successively subtracted value becomes the digital data at that point.

The digital data at each point in time becomes a digital data group corresponding to a waveform of a half cycle of a sine wave.

“Embodiment” An embodiment of the present invention will be described below based on the drawings.

1 to 3 show one embodiment of the present invention.

As shown in FIG. 2, the sine wave is assumed to be a pseudo sine wave. The pseudo sine wave has 5 in the positive half cycle.
The interval from 0 to π/4 has a slope of 3/π, and the interval from π/4 to 5π/12 has a slope of 3/2π.
, and the interval from 5π/12 to 7π/12 is 1,
The interval from 7π/12 to 3π/4 is set to have a slope of -3/2π, and the interval from 3π/4 to π is set to have a slope of -3/π.

Further, the half cycle of the positive area is divided into an addition area and a subtraction area, with the addition area being an area from 0 to π/2, and the subtraction area being an area from π/2 to π.

The negative half cycle is constructed by reversing the polarity of the positive half cycle.

FIGS. 2 and 3 show a circuit diagram and a timing chart of the digital sine wave generator, respectively.

In the digital sine wave generator, an oscillator 10 is connected to an up/down counter 3 via a digital circuit 20.
Connected to 0. Further, the up-down counter 30 is connected to a D/A converter 40 that outputs a sine wave.

If the sine wave output frequency is f ₀ , the frequency of the oscillator 10 is selected to be f ₀ ×12×2 ² ×2 ⁿ (n≧1).

The output terminal a of the oscillator 10 is connected to the output terminal a of the digital circuit 20.
It is connected to the input terminal of the advance counter 21. One output terminal d of the binary counter 21 is connected to the hexadecimal ring counter 22, and the other two output terminals b and c are connected to the hexadecimal ring counter 22.
They are connected to the input ends of NAND circuits 23 and 24, respectively.

The hexadecimal ring counter 22 has six output terminals e to j.
Each output terminal e to j has a binary counter 2.
It is ON for six consecutive pulses from 1 and OFF for the next six consecutive pulses, and each output terminal e to j is configured so that the ON and OFF sections are shifted by one pulse. It's on.

Output terminals e and i are input to a NOR circuit 25, respectively. The output end k and the output end g of the NOR circuit 25 are respectively input to the NOR circuit 26.

The output terminal g is input to the NAND circuit 23, and the NOR
The output terminal l of the circuit 26 is input to the NAND circuit 24. The output terminal m of the NAND circuit 23 is connected to the OR circuit 27 via the NOT circuit, and the output terminal n of the NAND circuit 24 is connected to the OR circuit 27 via the NOT circuit.
It is connected to the.

An output terminal o of the OR circuit 27 is connected to an up-down counter 30. That is, the output end m,
Output terminal o of OR circuit 27 except when both n are ON
is turned on and output to the up/down counter 30.

The up-down counter 30 is a D/A converter 40
It is connected to the. An output terminal j of the hexadecimal ring counter 22 is connected to an up-down counter 30 and also to a flip-flop 50. An output terminal p of the flip-flop 50 is connected to the D/A converter 40.

Next, the effect will be explained.

The output of the output terminal a of the oscillator 10 is the output of the binary counter 2.
The frequency is divided by 1 and becomes the output of each output terminal b, c, and d. The output from output end b has a frequency twice that of the output from output end c, and the output from output end d has a sufficiently low frequency of 2 ^m (m>3) relative to the output from output ends b and c.

In the hexadecimal ring counter 22, the signal at the output terminal d is
The frequency is divided by 12, and each output terminal e to j of the hexadecimal ring counter 22 outputs every π/12.

In the NOR circuit 25, the output of output terminal k is ON only when the outputs of output terminals e and i are both OFF,
In the NOR circuit 26, the outputs of the output terminals k and g are both
Only when it is OFF, the output of output terminal 1 will be ON.

In the NAND circuit 24, when the output terminal l and the output terminal c of the binary counter 21 are both other than ON, the output terminal n becomes ON, and in the NAND circuit 23, the output terminal g and the output terminal b of the binary counter 21 If both outputs are other than ON, output end m will be ON.

The AND circuit 27 combines the outputs of the output terminals m and n into a signal as the output of the output terminal o, and inputs the signal to the up-down counter 30 as a clock.

At this time, the up-down counter 30 receives the addition signal and the subtraction signal from the output terminal j of the hexadecimal ring counter 22, and if the addition signal is input, it adds the output signal from the output terminal o. Then, at the point of π/2, the addition signal is switched to the subtraction signal, and the output signal of the output terminal o is subtracted from the added value.

In other words, the added or subtracted values become sequential sine wave digital data.

At the same time, the flip-flop 50 divides the output signal of the output terminal j of the hexadecimal ring counter 22,
The output from the output terminal p becomes a +/- sign conversion signal and is input to the D/A converter 40. The D/A converter 40 converts the digital data into analog data and outputs a sine wave q.

For example, if the output of the output terminal p' shown in FIG. 3 is used, the D/A converter 40 outputs a single-phase fully rectified waveform q'.

In the up-down counter 22, the input frequency as a group of digital data corresponding to a half cycle of a sine wave has an interval of 2f, π/4 from 0 to π/4.
The interval from 4 to 5π/12 is f, the interval from 5π/12 to 7π/12 is 0, the interval from 7π/12 to 3π/4 is f, and 3π/
The interval from 4 to π is 2f.

A pseudo sine wave is output from the D/A converter 40, and this pseudo sine wave is expanded into a Fourier series and t
If the function y(t) is, it can be expressed as y(t)= _∞ 〓 ⁿ⁼¹ {(sin nπ/4+sin5nπ/12)6cosnωt/n ² π ² } n=1, 3, 5... Further, the amplitude value b(n) of each n-th harmonic can be expressed as b(n)=(sin nπ/4+sin5nπ/12)6/n ² π ² .

The strain rate D at this time can be determined by D={b ₍₃₎ ² +b ₍₅₎ ² +b ₍₇₎ ² +...} ^1/2 /b ₍₁₎ . The strain rate calculated from the above formula is D=1.6 (%). This distortion rate is sufficient to allow use as a pseudo sine wave.

In the above embodiment, the sine wave is a pseudo sine wave, and the range from 0 to π is divided into five sections, but the sections may be further divided.

According to the digital sine wave generator according to the embodiment, when applied to sine wave PWM control, since the peak part (5π/12 to 7π/12) of the sine wave is flat, sine wave-triangular wave comparison PWM control is possible. PWM
This has the practical advantage of reducing control errors.

"Effects of the Invention" According to the digital sine wave generator of the present invention, since the digital circuit is connected to the D/A converter via the up-down counter, a digital IC such as C-MOS is used in the digital circuit. This makes it possible to use a common power supply voltage of 5V or more, which is the same as D/A converters, for digital circuits, eliminates the need for interfaces, simplifies the configuration, and reduces costs. Further, a large noise margin can be secured, and a desired sine wave can be reliably obtained.

[Brief explanation of drawings]

1 to 3 show an embodiment of the present invention, FIG. 1 is a circuit diagram of a sine wave generator, FIG. 2 is an explanatory diagram of a pseudo sine wave, and FIG. 3 is a sine wave generator. This is the timing chart. 10... Oscillator, 20... Digital circuit, 30
...Up-down counter, 40...D/A converter, 50...Flip-flop.

Claims (1)

[Claims] 1. Generate two or more types of pulses with different frequencies based on a clock signal from an oscillator, divide a half cycle of a sine wave into a plurality of sections corresponding to the various pulses, and The cycle is divided into an addition section and a subtraction section, and the addition section generates an addition signal that is a signal for adding up the number of pulses generated in each section, and the subtraction section calculates the number of pulses. a digital circuit that generates a subtraction signal that is a signal for subtraction; and outputting a group of digital data corresponding to the waveform of the half cycle by adding or subtracting the number of pulses based on the addition signal and the subtraction signal. A digital sine wave generator comprising: an up/down counter; and a D/A converter that converts the digital data group into an analog value. 2. The digital sine wave generator according to claim 1, wherein the sign of the analog value is reversed to obtain an analog value of a half cycle opposite to the half cycle of the sine wave. 3. The digital sine wave generator according to claim 2, wherein one cycle of the sine wave is constituted by an analog value of a half cycle of the sine wave and an analog value of a half cycle opposite to the half cycle. Device.