SU1587638A1 - Coding device - Google Patents

Abstract

The invention relates to automation, computing and communication technology. Its use in digital (e.g., fiber optic) transmission systems improves the speed and simplifies the encoder. The latter contains a serial-to-parallel converter 1, a frequency divider 2, a multiplexer 3, a shaper of 4 addresses, a trigger 5, and a shaper of 6 clock pulses. A positive effect is achieved when coding with the code MB1S by eliminating the ROM required to convert the alphabetic codes. 5 ill., 1 tab.

Description

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i The image relates to automation, computer engineering and technology |: it can also be used in {digital transmission systems (for example, fiber optic) about

The purpose of the invention is to increase the speed and simplify the device.

Fig, 1 shows the functional diagram of the coding device; FIGS. 2-4 are examples of the implementation, respectively, of the frequency divider, the address former and the former: • new pulses in FIG. 5 — timing charts;

The encoder contains 1 | 1 converter 1 serial code into parallel, divisor -2 hours, multiplexer 3 $ shaper h addresses, trigger 5, shaper

0 tact pulses, information and clock inputs 7 and 8, and informational and clock outputs 9 and 10,

1 The 1-to-parallel-to-code converter in parallel represents a fobo (d1 + 1) -bit register (t is the input codeword size), the information inputs of the first m bits of which are combined, and the information | 1 | 1 input input of the last bit Looped to the inverse output of the previous ifo bit in accordance with the mBlC C code generation algorithm.

Consider an example of the device for the case of m 5o

Frequency divider 2 can represent a pulse counter () performed on triggers 11 and having a scaling factor of 5. FIG. 2 Indicates outputs 12 of divider 2. Former 4 addresses can be executed (fig.Z) on triggers 13 with appropriate clocking. . In FIG. 3, the outputs 14 of this former are indicated. .

The clock pulse shaper 6 contains (FIG. 4) the first and second front edge emitters 15 and 16, trigger 17, integrator 18, DC amplifier 19. controlled pulse generator 20, setpoint input 21 and zeroing input 22

Pulse repetition rate at generator output 20 -Sii times

higher than the pulse repetition frequency at the input 8 (1.2 times dl) /

The encoder works as follows

The information signals (FIG. 5a) are fed to the information input of the converter 1. The clock pulses with a frequency f arrive at the clock input 8. In this case, at the outputs of divider 2, a multiphase signal is generated at frequency f / 5 with shift f. This allows rewriting of information signals to converter 1 at low frequencies. Clock signals with frequency f are shown in fi-5b, phase shifts are also presented there for clarity p, Q, (3 (2i ui), corresponding to the appearance of a dummy signal at the corresponding output of divider 2; the first - fifth output of the converter 1 will contain the signals shown in FIG. 5c - w. Inverse signal. at the output of the fifth bit converter 1 (figo5z) The signal of the phase (G) at the output of the sixth bit of the converter (Fig. 5i). Clock signals with a frequency of 1.2 f from the output of the driver 6 clock pulses (Figure 3) are fed to the input of the generator .4, the output signals of which (at the outputs 14.1-14.3, FIG. 3) are shown in FIG. 5n. In this case, at the outputs of the imaging unit 4, the codes 010, 110, 011, 111, 001, 101, 01Oo oo are set up in cycles, which corresponds to sequences of natural numbers 2,3,6,7, 4,5,2, ", This sequence determines the order of connecting the outputs of the converter 1 to the information ones odes multiplexer 3 (see Table I)

Number of digits - yes converter 1 1

23456

Multiplexer 323 Input Index

6 745.,

The input numbers of the multiplexer 3 are shown by segments and numbering in FIG. 5b - and. The signal at the output of the multiplexer 3 (FIG. 5o) is stored for one clock cycle of the frequency l, 2f in the trigger 5 and arrives at the output 9 (fig. 5p),

For code 5B1C, inputs 21 and 22 of driver 6 are connected to third outputs of divider 2 and driver 4. In this case, selectors 15 and 16 form short pulses that set trigger I7, respectively, to

single and zero states. The output signal of the trigger 17 is integrated, amplified (elements 18 and 19 and is fed to the generator 20 to adjust the frequency of the generated pulses, i.e., in the driver 6, the phase self-tuning of the frequency l, 2f is carried out.

As can be seen from the timing diagrams, there is a sufficiently large margin for changing the phase of the signal with a frequency l, 2f with respect to the phase of the signal with a frequency f (more than a period), which leads to both an increase in speed and an increase in the reliability of the decoding device (at the receiving side of the transmission system).

Thus, due to the exclusion of the ROM, the necessary dp conversion of alphabetic codes, the device is simplified and its speed is improved.

Claims (1)

Invention Formula The encoder containing the frequency divider, the first - the m-th outputs of which (m - the width of the input code word j is connected to the clock inputs of the first - m-th bits of the sequential code to the parallel, information bits of the first 10 25 thirty, 587638 which bits are combined and are the information input of the device, the clock generator, the output of which is connected to the input of the address generator, you- the strokes of which are connected to the address inputs of the multiplexer, and the trigger, the output of which is the information output of the device, which, in order to improve speed and simplify the device, the inverse output of the th Yes, the serial to parallel converter is connected to the information input of its (t + 1) -th bit, the clock input of which is connected to the first output of the frequency divider, the input of which is the clock input of the device, the direct outputs of the first - (t + 1 ) th bit converter after The parallel code is connected to the corresponding information inputs of the multiplexer, the output of which is connected to the trigger information input, the clock input of which is connected to the output of the clock generator, which is the clock output of the device, the setup input and the zero input of the clock pulse generator connected to the corresponding outputs of the address generator and frequency divider. t5 20 FIG 2 Fi.g.b 27, five 17 22, sixteen Fig ;but 75 W FIG. five