JPS59221083A - Driving method of signal output circuit for charge coupled device - Google Patents

Abstract

PURPOSE:To reduce extremely reset noise and to exract a signal output of high quality out of a CCD circuit by actuating an MOSFET in a saturated area to use it as a precharge gate. CONSTITUTION:A final charge transfer stage 10 of a CCD contains a final charge store electrode 1, an output gate electrode 2, a floating gate electrode 3 and a reset gate electrode 4 which are successively arrayed on the surface of a semiconductor substrate (not shown in the diagram). The signal charge transferred via the charge transfer stages is stored under the electrode 1 and then shifted to a floating gate part under the electrode 3 through an area under the electrode 2. Then the signal charge is led outside through the electrode 3. Then an MOSFETM1 is actuated in a saturated area and used as a precharge gate. Thus the generation of preset noise is prevented and at the same time a potential produced by the precharge operation is stabilized. Thus it is possible to extract a signal output of high quality out of a CCD circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a charge coupled device (CCD) forming an image sensor, a memory, etc.
The present invention relates to a method of driving a signal output circuit in a device.

[Background technology and its problems]

Conventionally, CCD has been widely known as an element that basically operates as an analog photoresist that stores signal charges on the surface of a semiconductor substrate and sequentially transfers the signal charges, and is used as a delay line, memory, optical image sensor, etc. is used to form. In image sensors formed using this CCD, a signal output circuit consisting of multiple stages of source follower type buffer circuits connected in cascade is mounted on the same semiconductor substrate as the CCD circuit.
SPET: MOS Field Effect
The above CC
Signal charges are taken out from a floating gate provided at the final charge transfer stage of the D circuit via the signal output circuit. In addition, in the floating gate section of the final charge transfer stage of the CCD circuit, a precharge MO is provided to prevent this section from being charged up by unnecessary charges caused by dark current generation, etc.
A so-called precharge gate I section formed of S FET is provided.

Conventionally, MO8F and E, which form part of the precharge game 1,
The transistor T operates in the triode region by being turned on at predetermined intervals, usually at intervals of several tens of milliseconds or less, in order to relieve the potential increase due to leakage between the source and train. The floating gate section is precharged by applying a constant voltage from the outside.

By the way, when the floating strand 1 section is periodically precharged by the operation of the triode region of the MOS FET, -
A reset noise corresponding to L7F electric I/4 is generated, and this reset noise is superimposed on the signal output from the signal output circuit. Here, the above q is a charge element, C is a capacitance of floating dandruff = 1 parts, k is a Boltzmann constant, and T is an absolute temperature. Generally, the floating gate section has a capacitance C of about 002 to 01 pF', and generates noise of about 50 to 100 pF'.

For example, in an area image sensor formed with a CCD, precharging is normally performed once every horizontal scanning period lH or every frame scanning period IF.
The above-mentioned zero cent noise appears as horizontal lines in the image when precharging is performed at 11 (cycles), and appears as screen flicker when precharging at IF cycles, and is a cause of shading at the DC level due to dark current. becomes.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, the present invention prevents the generation of reset noise caused by the precharging in a CC circuit having a floating capacitor 1 that is periodically precharged as described above, thereby achieving extremely high quality. The purpose of this is to enable a signal output to be extracted from the CCD circuit power.

[Summary of the invention]

In order to achieve the above-mentioned object, a driving method for a signal output circuit of a charge-coupled device according to the present invention includes a field effect transducer that precharges a floating gate section provided at a final charge transfer stage at a predetermined period. In the signal output circuit of the charge-coupled device, a precharge clock for operating the field effect transistor in the saturation region is applied to the gate of the field effect transistor, and the field effect transistor is activated immediately before the signal charge is input to the floating gate section. The floating gate section is precharged by a transistor.

〔Example〕

Hereinafter, an embodiment of a method for driving a signal output circuit in a charge-coupled device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a circuit diagram showing the configuration of a CCD signal output circuit to which the present invention is applied, and FIG. 2 is a time chart for explaining the operation of the signal output circuit.

In this embodiment, the final charge transfer stage 10 of the CCD is:
A final charge storage electrode 1, an output gate electrode 2, a floating gate electrode 3, and a reset gate electrode 4 are arranged in sequence on the surface of a semiconductor substrate (not shown), and signals transferred via a previous charge transfer stage (not shown). Electric charges are accumulated under the final charge storage electrode 1, and the signal charges are transferred to the floating gate 1 section under the floating gate electrode 3 through the region under the output gate electrode 2, and the signal charges are transferred to the floating gate 1 section under the floating gate electrode 3. - It is designed to be derived from electrode 3.

Here, the output gate electrode 2 is the final charge storage electrode 1.
This is to prevent the transfer lock 96cK applied to the floating gate electrode 3 from being coupled to the floating gate electrode 3, and a constant DC voltage VOG slightly higher than the low level is applied to the transfer lock 960. ing.

Further, a reset clock signal □, which is for removing the reset gate charge and is synchronized with the transfer lock 96CK, is applied. Transfer lock 9 above
6cK and Q/reset clock OR have the same rising timing and transfer lock as shown in FIG. The duty ratio of K is 2:l, and the duty ratio of reset clock 9611 is 1=1.

In this embodiment, the final charge transfer stage 10
The signal charge derived from the floating gate electrode 3 is output as the signal ■. The signal output circuit 260 for outputting from the signal output terminal 30 as ut includes nine MO8PET
The source of the first MO8FETM+ and the gate of the second MO8FETM2 are connected to the floating furnace-1/electrode 3.

The second MO8FETM2 is the third MO8FETM
3 constitutes an input-side source follower as a load, and the connection point between the source and the drain of the third MO8FETM3 is connected to the fourth MO8FETM3 through a coupling capacitor C1.
OS FET M4 source and 6th MO8FE
Connected to the gate of TM6.

Further, the sixth MOS FET Ms is the fifth MOS FET Ms.
Impark is configured with the MOS FET Ms as a load, and its drain and the fifth MO8FET
A connection point with the source of M5 is connected to the gate of the eighth MOS FETMS via a coupling capacitor C2. The eighth MO8FETMa constitutes an output side source follower with the ninth MO8FETM9 as a load, and the source and the ninth MO8FET
The connection point with the train of E'l"Ms is the signal output terminal 30
It is connected to the.

In addition, the above 2. 5th and 8th MO8I”ETM2
, Ms, Ml Ha, 6 F Ray 7 Ni'
h A dynamic voltage VI)D is applied. In addition, the third
．． 6th and 9th MO8FET M3, Ms,
A drive voltage Vss is applied to each source of the MO.

And the third and ninth MO8FET M3.
A constant gate voltage VGGI is applied to each gate of the MO, so that it functions as a constant current source. Furthermore, the fifth MO8FETM5 has a constant gate voltage VGG2 applied to its gate, so that it functions as a constant current source.

Also, the above 1. 4th O,, t: Hig 70) MO8
FE'rMr, M4. Each of M7 functions as a precharge gate, and a precharge voltage Vp is applied to each drain. And the above first
And the seventh MO8FET Ml, M7 has the first precharge clock lp1 applied to each gate, and the fourth MO8FET M4 has the same gate as the first precharge clock lp1 applied to its gate. A second precharge clock 96P2 of phase is applied.

Here, the first and second precharge clocks +
2'p+ and 96pz are in phase with each other as shown in FIG. 2, and have a pulse width τ■ that is included within the pulse width τ0 of the above-mentioned reset clock 〆R,
"Second Book 1. 4th and 7th M OSF E TM
The potential for operating l, M4, and M7 in the saturation region (
It is set to Jl and To.

In this example, the first MO8FETM is:
After the signal charges in the floating furnace section 1 of the final charge transfer stage 10 of the CCD are removed by the above reset pulse, the next signal charges are transferred to the floating furnace section 1 of the final charge transfer stage 10 of the CCD.
The floating gate section is precharged by operating in the saturation region with the first precharge clock 96P□ until the signal charge is transferred to the first section, and the next signal charge is transferred to the floating gate section. It enters the OFF operating state immediately before being transferred. The first MO8FETM described above.

The potential of the floating furnace-1 under the electrode 3 connected to the source of the first MO8 is
Due to the precharge operation by FETM+, the MO8F
determined by the minimum potential of ETM+, and
Due to this operation and the dark current d constantly generated in the source region ζ of the MO8I''EFM, an amount of charge approximately proportional to the repetition time t of the precharge operation is accumulated, thereby stabilizing the charge.

and a first MO8T”ETM operating in the saturation region,
The amount of charge due to the dark current ■d generated in the source region is calculated as ■d゛t-8/q, where S is the area of the source region.
Therefore, the above precharge operation generates a reset noise of Ia-t (Ia-t) qelJ.

Here, in general, the dark current Id generated in the source region of MO8FET is about ~10 nA/cm, and the area S of the source region is about 300 to 600 μm'. If the sensor performs the precharge operation at the charge transfer period (70n(8)), the reset noise can be reduced to about 003 to o2ee, and even if the precharge operation is performed every IH, Reset noise can be suppressed to about 5 el.

Note that in the signal output circuit 20 shown in FIG. 1 above,
Each MO8El which constitutes the source follower of the input stage
M2. Ms, 408 to the valley that makes up Inpark.
FET Ms, M6, and each MOS FET Ms forming the source follower of the output stage.

Ms can be used to lower the surface channel MO8 as well as the buried chamfer. In this case, the threshold value VT of the FET
1. As I became Debresung Yong (-△■111:i
The output bias level of each north follower and impark becomes higher by 6~10■), and each coupling capacitor C1, C
It is necessary to stably perform the bias shift by 2. Therefore, in the signal output circuit 20, the fourth and seventh M
OS F J. Ji” M4.

In M7, the above-mentioned first Ms8 ]=N 'l'
By performing a precharge operation similar to M+,
This is intended to stabilize the bias and reduce noise. Generally, the signal output circuit in a CCD may employ a configuration in which an inverter is omitted, a configuration in which three or more stages of source followers are connected in cascade, or a configuration in which a sample bold circuit is incorporated. .

〔Effect of the invention〕

As is clear from the description of the embodiments described above, according to the present invention, by operating the Ms8 FET in the saturation region and working as a precharge gate 1, the operation in the conventional triode region is improved. Arose ↓, /Ck'r"
The reset noise can be removed to make the reset noise extremely small, and the potential due to the precharge operation can be stabilized, so that the intended purpose can be fully achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a CCI signal output circuit to which the present invention is applied. FIG. 2C is a time chart for explaining the operation of the first embodiment. 1...Final charge storage electrode 3...
・・・・・・Floating game 1・Electrode 10・
......Final charge transfer stage 20 of CCD...
......Signal output circuit 30...Signal output terminal M+......For precharging 408 1
"E'I" Patent Applicant Sony Corporation Agent Patent Attorney Kodo Koike 1) Toshiei - Procedural Amendment (Spontaneous) November 8, 1980 Commissioner of the Japan Patent Office Kazuo Wakasugi 1, Indication of the Case 1981 Patent Application No. 95570 2, Relationship with Title of Invention A'1 Special IR Applicant Address 6-7-35, Kitashinyo, Tokyo Parts Store Name (218) Sony Corporation (211'') Representative: Norio Ohga 4, Agent: 105 Address: 11 Mori Building IIIPL, 2-6-4 Toranomon, Minato-ku, Tokyo (508) 8266
No. 6, "Detailed Description of the Invention" of the specification subject to amendment (locks and drawings. 7. Contents of amendment C7-1) Statement on page 2, line 13 of the specification: "... Add "floating diffusion section or..." between "floating gate section..." and "floating gate section...". C7-2) The statement “Floating gate portion ((due to unnecessary charge)” from page 2, line 16 to line 17 of page 2 of the specification is corrected as follows. (7-3) The description on page 8, line 14 of the specification states, ``Constant current (7-4) In the specification, on the 7th line of the JIO page, between the statements "...determined," and "and..." C7-5) Correct Figure 2 of the attached drawings as shown in the attached sheet.

Claims (1)

[Claims] In a signal output circuit of a charge-coupled device equipped with a field effect transistor that precharges a floating capacitor 1 provided in the final charge transfer stage at a predetermined period, a precharge clock that operates the field effect transistor in a saturation region is used. is applied to the gate of the field effect i-rancisk so that the field effect transistor precharges the floating gate section immediately before a signal charge is input to the floating gate section 1. A method for driving a signal output circuit in a charge-coupled device, characterized by: