JPH01292856A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To increase a dynamic range of an element and to increase a smear suppressing ratio to realize high picture quality by setting a threshold voltage of a MOS transistor which constitutes a sample hold switch, a signal reading out switch, and a horizontal switch for line selection at a low level for an nMOS, and at a high level for a pMOS. CONSTITUTION:In an nMOS (Fig. b) which constitutes a sample hold switch, a reading out switch, and a horizontal switch, a high density p<+> layer 23 which is the same type of a substrate usually formed under a gate electrode 24 to increase a threshold voltage of the nMOS, is not provided under the gate electrode 24 of the sample hold switch, the reading out switch and the horizontal switch, and the threshold voltage of each of the above switches is made low. Since the threshold voltage of an nMOS (Fig. a) of the other part of an image sensing element is made the same as usual, malfunction is prevented. The on- resistance of the sample hold switch, the reading out switch, and the horizontal switch can be reduced in this way; therefore, the dynamic range of the element can be increased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a solid-state imaging device, particularly a highly sensitive solid-state imaging device.

The present invention relates to a solid-state imaging device suitable for achieving low smear.

[Conventional technology]

Conventionally, MO8 is a typical two-dimensional surface imaging device.
Solid-state imaging devices are known. (M.

Aoki at al Near Yesnis Sissi Digest of Technical Papers, p26゜F
eb, 13.1980). The above-mentioned conventional technology has a circuit configuration as shown in FIG. In Figure 9, 1 is 2
Photoelectric conversion elements (photodiodes) are arranged dimensionally and perform photoelectric conversion, 2 is a vertical scanning circuit that selects each row, 3 is a vertical gate line that guides the selection signal from the vertical scanning circuit 2 to each vertical switch, 4 is a vertical A vertical switch that opens and closes according to the selection signal from the scanning circuit 2, 5 a horizontal scanning circuit that selects each row, 6 a horizontal switch that opens and closes according to the selection signal from the horizontal scanning circuit 5, and 7 an amplifier circuit provided outside the element. , 8 are vertical signal lines, and 9 are horizontal signal lines. The above circuit performs the following operation. First, during the horizontal blanking period,
The voltage on the vertical gate line 3 of the row selected by the vertical scanning circuit 2 becomes high, the vertical switch 4 opens, and signal charges are sent from the photodiode 1 to the vertical signal line 8. after that,
During the horizontal scanning period, the horizontal scanning circuit 5 operates, the horizontal switches 6 sequentially open and close, and the signal charges are sequentially transferred to the horizontal signal line 9.
The signal is then amplified by an amplifier circuit 7 outside the element and output.

[Problems to be Solved by the Invention] The MO8 type solid-state image sensor described above has KT generated by thermal noise of the horizontal switch 6 when the horizontal switch 6 opens and closes.
No consideration is given to two points: C noise and noise from the external wideband amplifier 7, which is necessary for high-speed horizontal scanning. As a result, there were problems in that the noise was large and the signal-to-noise ratio (hereinafter referred to as S/N ratio) was low. moreover,
-Vertical signal line 8 due to light leakage etc. during horizontal scanning period
No consideration has been given to the smear phenomenon caused by excess charge generated within the camera, and bright lines that look like white tails may appear at the top and bottom of the reproduced image when capturing images under high illumination, that is, when photographing a bright subject. 1. There was a problem in that the image quality deteriorated significantly.

In contrast, each vertical signal line 8 is equipped with an amplifier circuit that detects and amplifies the potential of the vertical signal line 8 and a reset switch that resets the vertical signal line, so that the potential of the empty vertical signal line 8 after reset is By providing a means (hereinafter referred to as a correlated double sampling circuit) that detects the difference between the potential of the vertical signal line 8 when a signal is present and outputs only the true signal component, the noise and smear are reduced. The inventors of the present invention have proposed a solid-state image sensor (Japanese Patent Application No. 128123/1983).

FIGS. 10 to 11 are diagrams for explaining the operation of an example of this type of solid-state image sensor. This will be explained below according to the figures.

FIG. 10 shows a circuit configuration diagram of an embodiment of the solid-state imaging cord. In the figure, 1 to 6, 8 and 9 are the same as those in FIG. 71 is a preamplifier circuit for detecting and amplifying the potential of each vertical signal line; 72 is a self-bias switch for setting the amplification circuit 71 in a high gain region; and 74 is a coupling capacitor.

73 is a feedback capacitor, 75 is a clamp switch, 12 is a unity gain buffer amplifier, and 13 to 17 are unity gain buffers (Y, A,
IIAOUE et al: IE Journal of Solid State Circuits Vol, 5C-14, PP, 961-969. Dec
, ], 97'1 (IEEE J, 5solid-3tat
e C1rcuits, Vol, 5C-14゜pp,
961-969. 13 is a memory capacity, 14 is a sample hold switch for writing a signal to the memory capacity 13, 15 is a signal readout switch, 16 is a switch for offset cancellation, and 17 is an output buffer amplifier. , terminal ○UTI, 0
UT2 is an output terminal, and a bias voltage necessary for the operation of the unity gain puffer amplifier is applied to the terminal Vv. Further, FIG. 11 shows pulse timing for driving the element shown in FIG. 10. 81 to S5 are voltages applied to each terminal in FIG. Note that in this embodiment, each switch is an N-channel switch, and in the case of a P-channel switch, the polarity of the clock signal may be inverted. The operation of this embodiment will be explained below.

When entering the horizontal blanking period, first, the DC output voltage of each row when there is no signal charge and only smear charge is read into the memory capacity 13-1 of the unity gain buffer, 81. S2. S3. The potential of S5 goes high and switches 72, 75.14-1.16 open. At this time, the vertical signal line 8 is reset and the preamplifier 71 is biased to the high gain region. Further, the input terminal of the unity gain bath amplifier 12 is reset to the bias voltage Vv. Furthermore, the input terminal voltage of the output buffer amplifier 17 becomes the offset voltage of the output buffer amplifier 17 (tz in FIG. 11). Switch 72 is then closed and preamplifier 71 is activated. At this time, the vertical signal line fluctuates by vn due to the KTC noise, but since the switch 75 is open, this noise does not propagate beyond the buffer amplifier 12 (t z in Fig. 11).
5 closes and the unity gain buffer amplifier 12 is activated, and the potential fluctuation of the vertical signal line 8 after this time is transmitted to the memory capacitor 13-1 via the preamplifier 71 and the coupling capacitor 74° and the unity gain buffer 12. (ts in Figure 11).

After this, after a time period of Tsz has elapsed, the switch 14-
1 is closed and there is no signal charge and only smear charge, the DC output voltage of the buffer amplifier 12 is the memory capacity 13-
1 (1 in Figure 11).
4). Similarly, the DC output voltage when there is a signal charge and a smear charge is determined by the memory capacity 1 of the unity gain buffer.
Read out in 3-2. That is, switches 72, 75.1
4-2 is opened, and the vertical signal 1fA8 and the input terminal of the buffer amplifier 12 are reset. Then switch 72
．． 75 are closed in sequence, the potential of a certain vertical gate line 3 selected by the vertical scanning circuit 2 becomes high, the vertical switch 4 is opened, and signal charges are sent from the photodiode to the vertical signal line 8. After the time Ts2 has elapsed since the switch 75 was closed, the switch 14-2 is closed, and the DC output voltage of the unity gain buffer amplifier 12 when there is a signal charge and a smear charge is applied to one electrode of the memory capacitor 13-2. will be retained. After this, switch 16 closes,
The offset voltage of the output buffer amplifier 17 is held at the other electrodes of the memory capacitors 13-1 and 13-2.

When the horizontal scanning period begins, the signal of the unity gain buffer amplifier 12 held in each memory capacity and the DC output when there is a smear charge and when there is no signal and only a smear charge are sequentially read out. In other words, by the horizontal scanning circuit,
When a certain column (assumed to be column n) is selected, one of the two-phase pulses (φ or φ2) that drives the horizontal scanning circuit is selected.
), the horizontal switch 6-2 and readout switch 15-2 of the nth column open, and the signal of the buffer amplifier 12 when the terminal 0UT2 has the signal of the nth column held in the memory capacity 13-2 of the nth column is opened. The DC output voltage appears.

At the same time, the horizontal switch 6-1 and the readout switch 15-1 in the n+1 column are also opened, and the terminal OUT 1 is connected to the n+1
The DC output voltage of the buffer amplifier 12 when there is no signal charge in the n+1 column held in the column memory capacitor 13-1 is displayed. Therefore, the output voltage of terminal 0UT1 is set to 1 outside the element.
By delaying the clock signal and taking the difference from the output voltage of the terminal 0UT2, it is possible to obtain a true signal component that is free from potential fluctuations in the vertical signal line due to smear charges.

According to this embodiment, by providing a correlated double sampling circuit for each vertical signal line 8, it is possible to obtain a signal output free from KTC noise, which is one of the main noise sources of a conventional MO8 type solid-state image sensor. . In addition, by providing an amplifier circuit for each vertical signal line 8, the band required for the operation of the amplifier circuit can be made lower than the band required for the amplifier circuit of conventional elements, which is another main noise source of conventional elements. Amplifier noise can be significantly reduced. As a result, a high S/N can be achieved. Furthermore, the generation time of excess charge mixed into the signal is the time from when the self-bias switch 72 closes to when the sample-hold switch 14 closes, which can be significantly reduced compared to one horizontal scanning period in the conventional method. By independently reading the potential fluctuation of the vertical signal line due to the smear charge and the vertical signal line potential fluctuation due to the signal charge, and by taking the difference, a true signal without smear mixture is obtained, resulting in low smear. It is possible.

By the way, in the above-mentioned solid-state image sensor, the following two points have not been considered. Each point will be explained below.

First, in the solid-state imaging device, minute fluctuations in potential of the vertical signal line 8 are detected and amplified by the preamplifier 7 to reduce noise. Therefore, the signal voltage amplitude after the preamplifier 71 becomes large.

Therefore, when the output voltage of the unity gain buffer 12 becomes a high voltage, the sample hold switch 14. The on-resistance of the read switch 159 for reading signals from the memory capacity and the horizontal switch 6 for row selection becomes high, making it difficult to read signals. In particular, readout switch 15. The increase in the on-resistance of the horizontal switch 6 prevented the realization of high-speed horizontal scanning. As a result, there is a problem in that the signal voltage amplitude that can be read becomes small, and the dynamic range of the element is limited.

In the above embodiment, the case where the switch is an nMOS is described, but in the case of the PMO 8, a similar problem occurs when the output voltage of the unity gain buffer 12 becomes a low voltage.

Second, the memory capacity of the unity gain buffer is 13-
The output voltage of the smear charge held at 1 and the memory capacity 1
When obtaining the true signal component by reading out the output voltage of the signal charge mixed with the smear charge held in 3-2 during the horizontal scanning period and taking the difference between the two, the differential circuit is connected to the outside of the element. be. As a result, due to variations in the characteristics of the discrete electronic circuit components that make up the differential circuit and parasitic capacitance, the gain of the output signal from the memory capacitor to the differential circuit cannot be made the same, making it difficult to obtain a high smear suppression ratio. there were. The above two problems can be solved by setting up an amplifier for each pixel and a memory capacity for each vertical signal line as described in Japanese Patent Application No. 153292/1989 by the inventors of the present application. This problem is also common to devices that cancel variations in the DC output of the amplifier by holding the pixel amplifier output when there is no signal charge in the memory capacity and then providing means for taking the difference between the two.

The purpose of the present invention is the following two points. First, an amplifier is provided for each vertical signal line or each pixel, and after storing the signal output of each amplifier in the memory capacity provided for each vertical signal line, the memory capacity is sequentially selected and read out. In the solid-state imaging probe, the on-resistance of the sample hold switch for writing signals to each memory capacity, the readout switch for reading signals from each memory capacity, and the horizontal switch for row selection is lowered, and the readout of signals is improved. and expand the dynamic range of the device.

Second, an amplifier is provided for each vertical signal line or for each pixel, and the output of each amplifier when there is no signal and the output of each amplifier when there is a signal are read out independently.

By taking the difference, the objective is to improve the differential capability of a solid-state image sensor that obtains a true signal, increase the smear suppression capability or the effect of canceling variations in DC output, and achieve high image quality.

(Means for Solving Problem i1) The first purpose is to provide a sample hold switch for writing signals to each memory capacity, a read switch for reading signals from each memory capacity, and a horizontal By setting the threshold voltage of the MOS transistors constituting the switch lower than the threshold voltage of the MOS transistors constituting other parts of the imaging probe when each switch is an nMOS, and higher when each switch is a 9MO8. achieved.

Further, the second object is achieved by providing inside the element a differential circuit that takes the difference between when there is no signal and when there is a signal output from the amplifier.

[Effect]

First, the sample-and-hold switch, the readout switch, and the horizontal switch exhibit a small on-resistance when the switch is on, since each switch has a small threshold voltage in the case of nM OS or high in the case of p, Mo2. . In addition, when off, the source voltage of each of the three switches mentioned above is equal to the substrate voltage in the case of nMOS.
Since it is higher, or lower in the case of 9MO8, it is sufficiently turned off and does not malfunction.On the other hand, by keeping the threshold voltage of other parts of the image sensor at the same value as before, malfunction can be prevented. can. As a result, the on-resistance of the sample hold switch, readout switch, and horizontal switch can be lowered without causing the image sensor to malfunction, and the dynamic range of the element can be expanded.

Second, the differential circuit provided inside the element functions to make the gain the same when the output voltage of the smear electric charge is differentiated from the output voltage of the signal charge mixed with the smear charge. As a result, a high smear suppression ratio can be obtained, and high image quality can be achieved.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1(b) is a cross-sectional structural diagram of the nMOS that constitutes the sample hold switch, readout switch, and horizontal switch, and FIG. 1(a) is the nMOS of other parts of the image sensor.
It is a cross-sectional structure diagram of S. In the figure.

21 is a p-substrate, 22 is an nMOSMOS transistor,
n middle layer forming the drain, 23 is p middle layer, 24 is MO
A material constituting the electrode of the S transistor, for example, a polysilicon gate. In this embodiment, a p-middle layer 23 of the same type and high concentration as the substrate, which is usually formed under the gate electrode 24 in order to increase the threshold voltage of nMO8, is used. is not formed under the gate electrodes 24 of the sample hold switch, readout switch, and horizontal switch, thereby lowering the threshold voltage of each of the switches. This embodiment has the advantage that the threshold voltage of each switch can be lowered and the on-resistance can be lowered without forming a special impurity layer.

Next, another embodiment of the first invention will be described with reference to FIG. Figure 2(b) shows the nMOS that constitutes the sample hold switch, readout switch, and horizontal switch.
Figure (a) is a cross-sectional structural diagram of n of other parts of the image sensor.
FIG. 2 is a cross-sectional structural diagram of an MOS.

21 to 24 in the figure are the same as those in FIG. 1. In this embodiment,
By forming a low concentration n- layer 25 of a conductivity type opposite to that of the substrate under the gate electrode 24 of the sample hold switch, readout switch, and horizontal switch, the threshold voltage of each of the switches is lowered. In this embodiment, by appropriately setting the concentration of the n-layer 25, a desired threshold voltage can be obtained and the on-resistance of the switch can be lowered.

Furthermore, another embodiment of the first invention will be described with reference to FIG. Figure 3(b) shows the nMOS that constitutes the sample hold switch, readout switch, and horizontal switch.
Figure (a) is a cross-sectional structural diagram of n of other parts of the image sensor.
FIG. 2 is a cross-sectional structural diagram of an MOS.

In the figure, 21 to 24 are the same as in FIG. In this embodiment, by making the oxide film thickness t oxs under the gate electrode 24 of the sample hold switch, readout switch, and horizontal switch thinner than the oxide film thickness t OXN of other parts,
The threshold voltage of each switch is lowered. In this example, the case where the switch is nM OS is described, but 2M OS is used as the switch.
This embodiment is similarly effective in the case of O8.

Note that it is also possible to implement the above three embodiments in combination.

An embodiment in which each switch is an nMOS has been described above, but an embodiment in which each switch is 9MO5 will be described with reference to FIG. FIG. 4(b) is a cross-sectional structural diagram of the 2MO8 constituting the sample hold switch, readout switch, and horizontal switch, and FIG. 4(a) is a cross-sectional structural diagram of the 2MO8 of other parts of the imaging cord.

In the figure, 21, 23, and 24 are the same as in FIG.

26 is an n-well layer where pMos is formed, 27 is pMo
In this embodiment, the p+ middle layer 28 forming the source and drain of the S transistor is a p middle layer.

In order to lower the threshold voltage of 2MO8 to a range that does not cause device malfunction, a substrate with a higher concentration than the 2 layer 23 that is usually formed under the polysilicon gate and a p÷10 layer 8 of the opposite conductivity type are used.
By forming 2MO8 below the gate electrode 24 of each switch, the threshold voltage of 2MO8 constituting the switch is increased. In this embodiment, by appropriately setting the concentration of the p-type intermediate layer 28, a desired threshold voltage can be obtained and the on-resistance can be lowered.

Note that in order to lower or raise the threshold voltage of the MOS transistor, the channel length of the transistor of each switch may be made shorter than that of other parts of the element.

Now, the on-resistance of each switch is n M O
In the case of S, it can be reduced by lowering the threshold voltage of each transistor and lowering the DC output voltage of the unity gain buffer amplifier 12. FIG. 5 shows such an embodiment.

Figure 2 (a) is a circuit configuration diagram of a source follower that constitutes a unity gain buffer.
s driver, 30 is pMO8 load, VD is power supply voltage, V
s is ground voltage + Va is load bias voltage, vXN
represents the input voltage, and Voυ represents the output voltage. Further, FIG. 5(b) is a cross-sectional structural diagram of the pMOS driver shown in FIG. 5(a), and 21, 24°, 26, 27, 28 are the same as those in FIG. 4(b). FIG. 5(c) shows a sample hold switch,
n M O that constitutes the readout switch and horizontal switch
21, 22, and 24 are the cross-sectional structure diagrams of S.
). In this embodiment, in the same way as in FIG.
In addition to lowering the threshold voltage of the nMOS that constitutes each switch, the pMOS that constitutes the source follower driver is
Increase the threshold voltage of MO8.

By lowering the output voltage of the unity gain buffer 12, the on-resistance of the switch can be reduced.

Note that if the switch is pMO8, the driver pMO
It is sufficient to lower the threshold voltage of 8 and increase the output voltage of the unity gain buffer.

In addition, in the embodiments shown in FIGS. 1 to 5 above, the threshold voltages of the MOS transistors of the sample hold switch, readout switch, and horizontal switch were all changed, but depending on the balance with other functions, Only one or two may be changed.

Further, the first invention is similarly applicable to an image pickup device in which an amplifier is provided for each pixel as described in Japanese Patent Application No. 153292/1982.

FIG. 6 shows an embodiment of the second invention. In Fig. 6, 61, 62, 66 are sample and hold switches, 6
3 is a pump switch, 64 is a coupling capacitor, 65 is a unity gain buffer, and 67 is an output buffer. Also, OUT 1.

0UT2 is connected to ○UTI, 0UTI, - in FIG. φ1. φ2 indicates a horizontal scanning pulse having a phase difference of 180°.The operation of this circuit will be described below.

When entering the horizontal scanning period, n
For example, when a column is selected in synchronization with φ1, the output voltage when there is a signal mixed with n columns of smear in 0UT2 is 0.
The smear output voltage when there is no signal in the n+1 column appears in UT1. At this time, the sample switch 61-1 and the clamp switch 63-1 are turned on, and the smear output voltage of the n+1 column of 0UTI is held across the coupling capacitor 64-2 (1 = 1,).
When the +1 column is selected in synchronization with φ2, 0UT2 has the output voltage when there is a signal from the n+1 column, and 0UT1 has the output voltage when there is a signal from the n+1 column.
The smear output voltage when there is no signal in the +2 column is displayed.

At this time, the sample switch 62-2 is on and the clamp switch 63-1 is off, so at time ti φ1
n + held in the coupling capacitor 64-2 in synchronization with
The difference signal between the smear output voltage of one column and the signal output mixed with smear of the n + 1 column of OUT2, that is, n +
One row of true signal output is unity gain buffer 765-
2. Sample switch 66-2, external output buffer 67
is output to the outside of the element via. At the same time, sample switch 61-2 and clamp switch 63-2
is turned on, and ○UTI is connected to both ends of the coupling capacitor 64-1.
The smear output voltage of the n+2 columns of is held (t=tz)
. After that, when the n + 2 column is selected in synchronization with φl, the output voltage when there is a signal from the n + 2 column in 0UT2 is
○UTI shows the output voltage when there is no signal in the n+3 column. At this time, similarly to t=tl, the smear output of the n+2 column of 0UT1 is held across the coupling capacitor 64-2.

On the other hand, the sample switch 62-1 is turned on, the clamp switch 63-2 is turned off, and at 1 time tZ, the smear output voltage of the n+2 column held in the coupling capacitor 64-1 and the n+2 column of 0UT2 are synchronized with φ2. The difference signal of the signal output of,
That is, the true signal outputs of the n+2 columns are sent to the unity gain buffer 65-1, sample switch 66-1 . It is output to the outside of the element via the external output buffer 67 (1=t
s). Thereafter, the true signal output of each column is sequentially read out from the element in the same manner. According to this embodiment, the differential suppression ratio SR can be approximately expressed by equation (1).

...(1) Here, RB is the output resistance of the output buffer 12 provided for each column, and Rs is the clamp switch 63-1.63-2.
On resistance, Cc is the coupling capacitor 64-1.64-2
, CH is the capacitance value of the horizontal signal line 18, and tc is the on time of each switch. Further, the first term indicates a clamp error, and the second term indicates an error due to a difference in frequency characteristics due to a difference in load capacitance of the output buffer at the time of signal output and smear output. In this example, as a result of providing a differential circuit inside, C
The values of H and Cc can be made small, and a sufficient suppression ratio can be obtained.

Now, in the embodiment of FIG. 6, the output resistance of the output buffer 12 in each column is large, and the error in the second term of equation (1) may become large. In the embodiment of FIG.
By providing a voltage follower 68 at each input end as shown in the figure, the output buffer 12 at the time of signal output and smear output
The load capacitance of is made the same, and the error of the second term is reduced.

In the above embodiments, the case where a signal of one pixel in the vertical direction is read out has been described. On the other hand, in single-chip color solid-state image sensors, as a method to achieve high resolution and high image quality,
There are vertical and pixel readout methods. In the present invention, in order to realize this method, it is sufficient to provide a third memory capacity for holding the second signal for each column and perform the same operation.

however.

At this time, since the difference between the second signal and the smear signal is two clocks, it is necessary to delay the smear signal by one clock when taking the difference between the second signal and the smear signal. 8th
The figure shows an example in which vertical two-pixel readout is performed.

φ2 is the same as in FIG. 69 is a sample switch,
Reference numerals 81 to 85 constitute a unity gain buffer that performs offset cancellation to realize one clock delay, 81 is a read switch, 82 is a read switch, 83 is a sample switch, and 84 is an offset cancel switch.

85 is the memory capacity. The operation of this circuit is the same as that in Figure 7, except that when taking the difference between the second signal and the smear signal, the smear signal is delayed by one clock using a unity gain buffer composed of 81 to 85. It is.

It goes without saying that the second invention can be implemented regardless of the specific form of the differential circuit.

Further, the second invention is similarly applicable to an image pickup device in which an amplifier is provided for each pixel as described in Japanese Patent Application No. 153292/1982.

〔Effect of the invention〕

According to the present invention, first, the on-resistance of the sample hold switch for writing signals to the memory capacity, the read switch for reading signals from the memory capacity, and the horizontal switch for row selection can be reduced. This has the effect of expanding the dynamic range of the element.

Secondly, since the smear suppression ratio can be increased,
A solid-state image sensor with a large number of pixels can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the first invention, FIGS. 2, 3, and 4 are diagrams showing other embodiments of the first invention, and FIG. 5(c) is a diagram showing a circuit configuration of a source follower constituting a unity gain buffer according to an embodiment of the first invention, FIG. 5(b) is a diagram showing a cross section of a source follower driver, and FIG. ) is a diagram showing a cross section of the switch, FIGS. 6, 7, and 8 are diagrams showing the circuit configuration of the second invention, and FIGS. 9, 10, and 11 are diagrams showing the conventional MO
FIG. 3 is a diagram showing a circuit configuration of a type 3 element. 6...Horizontal switch, 13...Memory capacity, 14.
...sample hold switch, 15...signal readout switch, 21...p substrate, 22...n+ middle layer 23...2 layer, 25...n- layer, 26...n well layer , 27...p+ middle layer 28...p middle layer, 61,
62.66... Sample switch, 63... Clamp switch, 64... Coupling capacitor, 65... Unity gain buffer, 67... External output buffer, 68... Voltage follower, 69...・Sample switch, 81...Reading switch, 82...
Readout switch, 83...Sample switch, 84
...Offset cancel switch, 85...Memory capacity.

Claims (1)

[Claims] 1. A plurality of photoelectric conversion elements arranged on the same semiconductor substrate, a plurality of amplifiers that detect the photocharges of the photoelectric conversion elements and convert them into signal voltages, and a a plurality of memory capacities for holding time, a switch for writing signals to the memory capacity, a readout switch from the memory capacity, a scanning circuit for selecting the memory capacity, and a switch for writing signals to the memory capacity; a scanning circuit for selecting the memory capacity; In a solid-state imaging device comprising a selection switch that opens and closes in response to a signal, the threshold voltage of a MOS transistor constituting at least one of a switch for writing a signal into the memory capacity, a switch for reading from the memory capacity, and the selection switch is , a solid-state imaging device characterized in that the threshold voltage is different from that of a MOS transistor constituting other circuit elements. 2. It has a plurality of photoelectric conversion elements arranged on the same semiconductor substrate and a plurality of amplifiers for detecting the photocharges of the photoelectric conversion elements and converting them into signal voltages, and when there is a signal charge of the amplifiers. In a solid-state imaging device, the solid-state imaging device is provided with a means for independently reading the output when there is no signal charge and the output when there is no signal charge, and obtaining a difference between the two outputs, wherein the means for obtaining the difference between the two outputs is formed on the same semiconductor substrate. A solid-state imaging device characterized by: